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order number: 290701, revision: 015 07-dec-2005 intel? wireless flash memory (w18) 28f320w18, 28f640w18, 28f128w18 datasheet product features the intel ? wireless flash memory (w18) device with flexible multi-partition dual-operation architecture, provides high-performance asynchronous and synchronous burst reads. it is an ideal memory for low-voltage burst cpus. combining high read performance with flash memory intrinsic non-volatility, the w18 device eliminates the traditional system-performance paradigm of shadowing redundant code memory from slow nonvolatile storage to faster execution memory. it reduces total memory requirement that increases reliability and reduces overall system power consumption and cost. the w18 device?s flexible multi-partition architecture allows program or erase to occur in one partition while reading from another partition. this allows for higher data write throughput compared to single-partition architectures and designers can choose code and data partition sizes. the dual-operation architecture allows two processors to interleave code operations while program and erase operations take place in the background. high performance read-while-write/ erase ? burst frequency at 66 mhz (zero wait states) ? 60 ns initial access read speed ? 11 ns burst mode read speed ? 20 ns page mode read speed ? 4-, 8-, 16-, and continuous-word burst mode reads ? burst and page mode reads in all blocks, across all partition boundaries ? burst suspend feature ? enhanced factory programming at 3.1 s/word security ? 128-bit otp protection register: 64 unique pre-programmed bits + 64 user-programmable bits ? absolute write protection with v pp at ground ? individual and instantaneous block locking/unlocking with lock-down capability quality and reliability ? temperature range: ?40 c to +85 c ? 100k erase cycles per block ? 90 nm etox? ix process ? 130 nm etox? viii process architecture ?multiple 4-mbit partitions ?dual operation: rww or rwe ?parameter block size = 4-kword ?main block size = 32-kword ?top or bottom parameter devices ?16-bit wide data bus software ?5 s (typ.) program and erase suspend latency time ?flash data integrator (fdi) and common flash interface (cfi) compatible ?programmable wait signal polarity packaging and power ?90 nm: 32- and 64-mbit in vf bga ?130 nm: 32-, 64-, and 128-mbit in vf bga; 128-mbit in quad+ package ?56 active ball matrix, 0.75 mm ball- pitch ?v cc = 1.70 v to 1.95 v ?v ccq (90 nm) = 1.70 v to 1.95 v ?v ccq (130 nm) = 1.70 v to 2.24 v or 1.35 v to 1.80 v ?v ccq (130 nm) = 1.35 v to 2.24 v ?standby current (130 nm): 8 a (typ.) ?read current: 8 ma (4-word burst, typ.)
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intel? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 3 contents 1.0 introduction ............................................................................................................................... 9 1.1 nomenclature ................................................................................................................ ....... 9 1.2 conventions................................................................................................................. .........9 2.0 functional overview ............................................................................................................11 2.1 memory map and partitioning.............................................................................................12 3.0 package information ............................................................................................................15 3.1 w18 - 90 nm lithography ................................................................................................... 15 3.2 w18 - 130 nm lithography .................................................................................................16 4.0 ballout and signal descriptions ......................................................................................18 4.1 signal ballout .............................................................................................................. ........18 4.2 signal descriptions ......................................................................................................... ....20 5.0 maximum ratings and operating conditions ...........................................................24 5.1 absolute maximum ratings ................................................................................................24 5.2 operating conditions ........................................................................................................ ..25 6.0 electrical specifications .....................................................................................................26 6.1 dc current characteristics .................................................................................................2 6 6.2 dc voltage characteristics.................................................................................................2 8 7.0 ac characteristics ................................................................................................................29 7.1 ac write characteristics .................................................................................................. .41 7.2 erase and program times..................................................................................................47 7.3 reset specifications ........................................................................................................ ... 48 7.4 ac i/o test conditions ...................................................................................................... .49 7.5 device capacitance.......................................................................................................... ..50 8.0 power and reset specifications .....................................................................................51 8.1 active power................................................................................................................ .......51 8.2 automatic power savings (aps) ........................................................................................51 8.3 standby power ............................................................................................................... ....51 8.4 power-up/down characteristics.........................................................................................51 8.4.1 system reset and rst# ....................................................................................... 52 8.4.2 vcc, vpp, and rst# transitions .........................................................................52 8.5 power supply decoupling...................................................................................................52 9.0 bus operations overview ..................................................................................................53 9.1 bus operations .............................................................................................................. ..... 53 9.1.1 reads ....................................................................................................................5 3 9.1.2 writes.................................................................................................................... .54 9.1.3 output disable .......................................................................................................54 9.1.4 burst suspend .......................................................................................................54 9.1.5 standby..................................................................................................................5 5 9.1.6 reset ..................................................................................................................... 55
intel? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 4 order number: 290701, revision: 014 9.2 device commands ............................................................................................................. 55 9.3 command sequencing ....................................................................................................... 59 10.0 read operations .................................................................................................................... 60 10.1 asynchronous page read mode........................................................................................ 60 10.2 synchronous burst read mode.......................................................................................... 60 10.3 read array................................................................................................................. ......... 61 10.4 read identifier ............................................................................................................ ........ 61 10.5 cfi query .................................................................................................................. ......... 62 10.6 read status register....................................................................................................... ... 62 10.7 clear status register...................................................................................................... .... 64 11.0 program operations ............................................................................................................. 65 11.1 word program ............................................................................................................... ..... 65 11.2 factory programming ........................................................................................................ .66 11.3 enhanced factory program (efp) ..................................................................................... 67 11.3.1 efp requirements and considerations ................................................................ 67 11.3.2 setup .................................................................................................................... .68 11.3.3 program .................................................................................................................6 8 11.3.4 verify................................................................................................................... ... 68 11.3.5 exit..................................................................................................................... .... 69 12.0 program and erase operations .......................................................................................71 12.1 program/erase suspend and resume............................................................................... 71 12.2 block erase................................................................................................................ ......... 73 12.3 read-while-write and read-while-erase.......................................................................... 75 13.0 security modes ....................................................................................................................... 77 13.1 block lock operations...................................................................................................... .. 77 13.1.1 lock ..................................................................................................................... .. 78 13.1.2 unlock................................................................................................................... .78 13.1.3 lock-down............................................................................................................. 78 13.1.4 block lock status .................................................................................................. 79 13.1.5 lock during erase suspend ..................................................................................79 13.1.6 status register error checking ............................................................................. 79 13.1.7 wp# lock-down control .......................................................................................80 13.2 protection register ........................................................................................................ ..... 80 13.2.1 reading the protection register............................................................................ 81 13.2.2 programing the protection register....................................................................... 81 13.2.3 locking the protection register............................................................................. 82 13.3 vpp protection ............................................................................................................. ......83 14.0 set read configuration register .................................................................................... 84 14.1 read mode (rcr[15])........................................................................................................ 86 14.2 first access latency count (rcr[13:11])................ .......................................................... 86 14.2.1 latency count settings.......................................................................................... 87 14.3 wait signal polarity (rcr[10])...... .................................................................................... 88 14.4 wait signal function....................................................................................................... .. 88 14.5 data hold (rcr[9])......................................................................................................... .... 89 14.6 wait delay (rcr[8]) ........................................................................................................ .90 14.7 burst sequence (rcr[7])................................................................................................... 9 0
intel? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 5 14.8 clock edge (rcr[6]) ....... ................................................................................................. ..91 14.9 burst wrap (rcr[3])........................................................................................................ ... 92 14.10 burst length (rcr[2:0]) ................................................................................................... ..92 appendix a write state machine states ............................................................................93 appendix b common flash interface (cfi) .....................................................................96 appendix c ordering information ......................................................................................105
intel? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 6 order number: 290701, revision: 014 revision history date revision description 09/13/00 -001 initial release 01/29/01 -002 deleted 16-mbit density revised adv#, section 2.2 revised protection registers , section 4.16 revised program protection register , section 4.18 revised example in first access latency count , section 5.0.2 revised figure 5, data output with lc setting at code 3 added wait signal function , section 5.0.3 revised wait signal polarity , section 5.0.4 revised data output configuration , section 5.0.5 added figure 7, data output configuration with wait signal delay revised wait delay configuration , section 5.0.6 changed v ccq spec from 1.7 v ? 1.95 v to 1.7 v ? 2.24 v in section 8.2, extended temperature operation changed i ccs spec from 15 a to 18 a in section 8.4, dc characteristics changed i ccr spec from 10 ma (clk = 40 mhz, burst length = 4) and 13 ma (clk = 52 mhz, burst length = 4) to 13 ma, and 16 ma respectively in section 8.4, dc characteristics changed i ccws spec from 15 a to 18 a in section 8.4, dc characteristics changed i cces spec from 15 a to 18 a in section 8.4, dc characteristics changed t chqx spec from 5 ns to 3 ns in section 8.6, ac read characteristics added figure 25, wait signal in synchronous non-read array operation waveform added figure 26, wait signal in asynchronous page mode read operation waveform added figure 27, wait signal in asynchronous single word read operation waveform revised appendix e, ordering information 06/12/01 -003 revised entire section 4.10, enhanced factory program command (efp) and figure 6, enhanced factory program flowchart revised section 4.13, protection register revised section 4.15, program protection register revised section 7.3, capacitance, to include 128-mbit specs revised section 7.4, dc characteristics, to include 128-mbit specs revised section 7.6, ac read characteristics, to include 128-mbit device specifications added t vhgl spec in section 7.6, ac read characteristics revised section 7.7, ac write characteristics , to include 128-mbit device specifications minor text edits
intel? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 7 04/05/02 -004 new sections organization added 16-word burst feature added burst suspend section revised block locking state diagram revised active power section revised automatic power savings section revised power-up/down operation section revised extended temperature operation added 128 mb dc characteristics table added 128 mb ac read characteristics revised table 17. test configuration component values for worst case speed conditions added 0.13 m product dc and ac read characteristics revised ac write characteristics added read to write and write to read transition waveforms revised reset specifications various text edits 10/10/02 -005 various text edits updated latency count section, including adding latency count tables added section 8.4 wait function and wait summary table updated package drawing and dimensions 11/12/02 -006 various text clarifications 01/14/03 -007 removed intel burst order revised table 10 ?dc current characteristics? various text edits 03/21/03 -008 revised table 22, read operations, t apa added note to table 15, configuration register descriptions added note to section 3.1.1, read 12/17/03 -009 updated block-lock operations (section 7.1 and figure 11) updated table 21 (128 mb i ccr ) updated table 4 (wait behavior) added quad+ ballout, package mechanicals, and order information various text edits including latest product-naming convention 02/12/04 -010 added 90 nm product line removed bga* package added page- and burst-mode descriptions minor text edits 05/06/04 -011 fixed omitted text for table 21, note 1 regarding max dc voltage on i/o pins removed extended i/o supply voltage for 90 nm products minor text edits 06/03/04 -012 updated the title and layout of the datasheet date revision description
intel? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 8 order number: 290701, revision: 014 06/29/04 -013 v ccq max. changed for 90 nm products updated ?absolute maximum ratings? table typical i ccs updated as 35 a updated subtitle 01/21/05 -014 typical i ccs updated as 22 a minor text edits 07-dec-2005 -015 typical 90nm aps updated to 22 a in table 9 ?dc current characteristics? on page 26 . updated 90nm v lko to 0.7 v in table 10 ?dc voltage characteristics? on page 28 . product ordering information updated to w in table 47 ?w18 family: available product ordering information? on page 106 . date revision description
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 9 1.0 introduction this datasheet contains information about the intel ? wireless flash memory (w18) device family. this section describes nomenclature used in the datasheet. section 2.0 provides an overview of the w18 flash memory device. section 6.0 , section 7.0 , and section 8.0 describe the electrical specifications for extended temperature product offerings. ordering information can be found in appendix c . 1.1 nomenclature acronyms that describe product features or usage are defined here: 1.2 conventions the following list describes abbreviated terms and phrases used throughout this document: aps automatic power savings bba block base address cfi common flash interface cui command user interface du don?t use efp enhanced factory programming fdi flash data integrator nc no connect otp one-time programmable pba partition base address rcr read configuration register rwe read-while-erase rww read-while-write scsp stacked chip scale package srd status register data vf bga very-thin, fine-pitch, ball grid array wsm write state machine ?1.8 v? refers to the full v cc voltage range of 1.7 v ? 1.95 v (except where noted) and ?v pp = 12 v? refers to 12 v 5%. set refers to registers means the bit is a logical 1 and cleared means the bit is a logical 0. pin and signal often used interchangeably to refer to the external signal connections on the package ( ball is the term used for vf bga).
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 10 order number: 290701, revision: 015 throughout this document, references are made to top, bottom, parameter, and partition. to clarify these references, the following conventions have been adopted: word 2 bytes or 16 bits. signal names are in all caps (see section 4.2, ?signal descriptions? on page 20 .) voltage applied to the signal is subscripted for example v pp . block a group of bits (or words) that erase simultaneously with one block erase instruction. main block contains 32-kwords. parameter block contains 4-kwords. block base address (bba) the first address of a block. partition a group of blocks that share erase and program circuitry and a common status register. partition base address (pba) the first address of a partition. for example, on a 32-mbit top-parameter device partition number 5 has a pba of 0x140000. top partition located at the highest physical device address. this partition may be a main partition or a parameter partition. bottom partition located at the lowest physical device address. this partition may be a main partition or a parameter partition. main partition contains only main blocks. parameter partition contains a mixture of main blocks and parameter blocks. top parameter device (tpd) has the parameter partition at the top of the memory map with the parameter blocks at the top of that partition. this was formerly referred to as a top-boot device. bottom parameter device (bpd) has the parameter partition at the bottom of the memory map with the parameter blocks at the bottom of that partition. this was formerly referred to as a bottom-boot block flash device.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 11 2.0 functional overview this section provides an overview of the w18 device features and architecture. the w18 device provides read-while-write (rww) and read-white-erase (rwe) capability with high-performance synchronous and asynchronous reads on package-compatible densities with a 16-bit data bus. individually-erasable memory blocks are optimally sized for code and data storage. eight 4-kword parameter blocks are located in the parameter partition at either the top or bottom of the memory map. the rest of the memory array is grouped into 32-kword main blocks. the memory architecture for the w18 device consists of multiple 4-mbit partitions, the exact number depending on device density. by dividing the memory array into partitions, program or erase operations can take place simultaneously during read operations. burst reads can traverse partition boundaries, but user application code is responsible for ensuring that they don?t extend into a partition that is actively programming or erasing. although each partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in a read mode. augmented erase-suspend functionality further enhances the rww capabilities of this device. an erase can be suspended to perform a program or read operation within any block, except that which is erase-suspended. a program operation nested within a suspended erase can subsequently be suspended to read yet another memory location. after device power-up or reset, the w18 device defaults to asynchronous page-mode read configuration. writing to the device?s read c onfiguration register (rcr) enables synchronous burst-mode read operation. in synchronous mode, the clk input increments an internal burst address generator. clk also synchronizes the flash memory with the host cpu and outputs data on every, or on every other, valid clk cycle after an initial latency. a programmable wait output signals to the cpu when data from the flash memory device is ready. in addition to its improved architecture and interface, the w18 device incorporates enhanced factory programming (efp), a feature that enables fast programming and low-power designs. the efp feature provides the fastest currently-available program performance, which can increase a factory?s manufacturing throughput. the device supports read operations at 1.8 v and erase and program operations at 1.8 v or 12 v. with the 1.8 v option, vcc and vpp can be tied together for a simple, ultra-low-power design. in addition to voltage flexibility, the dedicated vpp input provides complete data protection when v pp v pplk . this device (130 nm) allows i/o operation at voltages lower than the minimum v ccq of 1.70 v. this extended v ccq range, 1.35 v ? 1.8 v, permits even greater system design flexibility. a 128-bit protection register enhances the user?s ability to implement new security techniques and data protection schemes. unique flash device identification and fraud-, cloning-, or content- protection schemes are possible through a combinat ion of factory-programmed and user-otp data cells. zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. an additional block lock-down capability provides hardware protection where software commands alone cannot change the block?s protection status.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 12 order number: 290701, revision: 015 the command user interface (cui) is the system processor?s link to internal flash memory operation. a valid command sequence written to the cui initiates device write state machine (wsm) operation that automatically executes the algorithms, timings, and verifications necessary to manage flash memory program and erase. an internal status register provides ready/busy indication results of the operation (success, fail, and so on). three power-saving features? automatic power savings (aps), standby, and rst# ? can significantly reduce power consumption. the device automatically enters aps mode following read cycle completion. standby mode begins when the system deselects the flash memory by de-asserting ce#. driving rst# low produces power savings similar to standby mode. it also resets the part to read-array mode (important for system-level reset), clears internal status registers, and provides an additional level of flash write protection. 2.1 memory map and partitioning the w18 device is divided into 4-mbit physical partitions, which allows simultaneous rww or rwe operations and allows users to segment code and data areas on 4-mbit boundaries. the device?s memory array is asymmetrically blocked, which enables system code and data integration within a single flash device. each block can be erased independently in block erase mode. simultaneous program and erase operations are not allowed; only one partition at a time can be actively programming or erasing. see table 1, ?bottom parameter memory map? on page 13 and table 2, ?top parameter memory map? on page 14 . the 32-mbit device has eight partitions, the 64-mbit device has 16 partitions, and the 128-mbit device has 32 partitions. each device density contains one parameter partition and several main partitions. the 4-mbit parameter partition contains eight 4-kword parameter blocks and seven 32- kword main blocks. each 4-mbit main partition contains eight 32-kword blocks each. the bulk of the array is divided into main blocks that can store code or data, and parameter blocks that allow storage of frequently updated small parameters that are normally stored in eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. ..
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 13 table 1. bottom parameter memory map size (kw) blk # 32-mbit blk # 64-mbit blk # 128-mbit main partitions sixteen partitions 32 262 7f8000-7fffff .. . .. . .. . 32 135 400000-407fff eight partitions 32 134 3f8000-3fffff 134 3f8000-3fffff .. . .. . .. . .. . .. . 32 71 200000-207fff 71 200000-207fff four partitions 32 70 1f8000-1fffff 70 1f8000-1fffff 70 1f8000-1fffff .. . .. . .. . .. . .. . .. . .. . 32 39 100000-107fff 39 100000-107fff 39 100000-107fff one partition 32 38 0f8000-0fffff 38 0f8000-0fffff 38 0f8000-0fffff .. . .. . .. . .. . .. . .. . .. . 32 31 0c0000-0c7fff 31 0c0000-0c7fff 31 0c0000-0c7fff one partition 32 30 0b8000-0bffff 30 0b8000-0bffff 30 0b8000-0bffff .. . .. . .. . .. . .. . .. . .. . 32 23 080000-087fff 23 080000-087fff 23 080000-087fff one partition 32 22 078000-07ffff 22 078000-07ffff 22 078000-07ffff .. . .. . .. . .. . .. . .. . .. . 32 15 040000-047fff 15 040000-047fff 15 040000-047fff parameter partition one partition 32 14 038000-03ffff 14 038000-03ffff 14 038000-03ffff .. . .. . .. . .. . .. . .. . .. . 32 8 008000-00ffff 8 008000-00ffff 8 008000-00ffff 4 7 007000-007fff 7 007000-007fff 7 007000-007fff .. . .. . .. . .. . .. . .. . .. . 4 0 000000-000fff 0 000000-000fff 0 000000-000fff
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 14 order number: 290701, revision: 015 table 2. top parameter memory map size (kw) blk # 32-mbit blk # 64-mbit blk # 128-mbit parameter partition one partition 4 70 1ff000-1fffff 134 3ff000-3fffff 262 7ff000-7fffff .. . .. . .. . .. . .. . .. . .. . 4 63 1f8000-1f8fff 127 3f8000-3f8fff 255 7f8000-7f8fff 32 62 1f0000-1f7fff 126 3f0000-3f7fff 254 7f0000-7f7fff .. . .. . .. . .. . .. . .. . .. . 32 56 1c0000-1c7fff 120 3c0000-3c7fff 248 7c0000-7c7fff main partitions one partition 32 55 1b8000-1bffff 119 3b8000-3bffff 247 7b8000-7bffff .. . .. . .. . .. . .. . .. . .. . 32 48 18000-187fff 112 380000-387fff 240 780000-787fff one partition 32 47 178000-17ffff 111 378000-37ffff 239 778000-77ffff .. . .. . .. . .. . .. . .. . .. . 32 40 140000-147fff 104 340000-347fff 232 740000-747fff one partition 32 39 138000-13ffff 103 338000-33ffff 231 738000-73ffff .. . .. . .. . .. . .. . .. . .. . 32 32 100000-107fff 96 300000-307fff 224 700000-707fff four partitions 32 31 0f8000-0fffff 95 2f8000-2fffff 223 6f8000-6fffff .. . .. . .. . .. . .. . .. . .. . 32 0 000000-007fff 64 200000-207fff 192 600000-607fff eight partitions 32 63 1f8000-1fffff 191 5f8000-5fffff .. . .. . .. . .. . .. . 32 0 000000-007fff 128 400000-407fff sixteen partitions 32 127 3f8000-3fffff .. . .. . .. . 32 0 000000-007fff
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 15 3.0 package information 3.1 w18 - 90 nm lithography figure 1. 32- and 64-mbit vf bga package drawing table 3. 32- and 64-mbit vf bga package dimensions dimension symbol millimeters inches min nom max min nom max package height a - - 1.000 - - 0.0394 ball height a 1 0.150 - - 0.0059 - - package body thickness a 2 - 0.665 - - 0.0262 - ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body width d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body length e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch [e] - 0.750 - - 0.0295 - ball (lead) count n - 56 - - 56 - seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 distance along d s 1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 distance along e s 2 2.150 2.250 2.350 0.0846 0.0886 0.0925 e seating plane top v iew - bump side down bot tom vie w - ba ll sid e up y a a1 d a2 2 ball a1 corne r 87654321 a b c d e f g s 1 s e b ball a1 corner 8 7 6 5 4 3 2 1 a b c d e f g
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 16 order number: 290701, revision: 015 3.2 w18 - 130 nm lithography figure 2. 32-, 64-, and 128-mbit vf bga package drawing table 4. 32-, 64-, and 128-mbit vf bga package dimensions dimension symbol millimeters inches min nom max min nom max package height a - - 1.000 - - 0.0394 ball height a 1 0.150 - - 0.0059 - - package body thickness a 2 - 0.665 - - 0.0262 - ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body width (32/64-mbit) d 7.600 7.700 7.800 0.2992 0.3031 0.3071 package body width (128-mbit) d 10.900 11.000 11.100 0.4291 0.4331 0.4370 package body length (32/64/128-mbit) e 8.900 9.000 9.100 0.3504 0.3543 0.3583 pitch [e] - 0.750 - - 0.0295 - ball (lead) count n - 56 - - 56 - seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 distance along d (32/64-mbit) s 1 1.125 1.225 1.325 0.0443 0.0482 0.0522 corner to ball a1 distance along d (128-mbit) s 1 2.775 2.2875 2.975 0.1093 0.1132 0.1171 corner to ball a1 distance along e (32/64/128-mbit) s 2 2.150 2.250 2.350 0.0846 0.0886 0.0925 e seating plane top v iew - bump s ide down bottom view - ball side up y a a1 d a2 2 ball a1 corner 87654321 a b c d e f g s 1 s e b ball a1 corner 8 7 6 5 4 3 2 1 a b c d e f g
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 17 figure 3. 128-mbit quad+ package drawing millimeters inches di me ns i ons s ymbol mi n nom max note s mi n nom max package height a 1.200 0.0472 ball height a1 0.200 0.0079 package body thickness a2 0.860 0.0339 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 9.900 10.000 10.100 0.3898 0.3937 0.3976 package body width e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 88 88 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 distance along d s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 top view - ball down bottom view - ball up a a2 d e y a1 drawing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 12345678
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 18 order number: 290701, revision: 015 4.0 ballout and signal descriptions 4.1 signal ballout the w18 device is available in a 56-ball vf bga and bga chip scale package with 0.75 mm ball pitch, or the 88-ball (80 active balls) quad+ scsp package. figure 4 shows the device ballout for the vf bga package. figure 5 shows the device ballout for the quad+ package. figure 4. 56-ball vf bga ballout notes: 1. on lower density devices, upper address balls can be treated as nc. (example: for 32-mbit density, a21 and a22 are nc). 2. see section 3.0, ?package information? on page 15 for mechanical specifications for the package. a b c d e f g a b c d e f g top view - ball side down complete ink mark not shown 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 bottom view - ball side up a4 a6 a18 vpp vcc vss a8 a11 a3 a5 a17 rst# clk a20 a9 a12 a2 a7 we# adv# a19 a10 a13 a1 a14 wp# dq12 a16 wait a15 a0 ce# dq1 dq2 dq4 dq6 dq15 vccq oe# dq0 dq9 dq10 dq11 dq13 dq14 vss vssq dq8 vccq dq3 vcc dq5 vssq dq7 a22 a21 a4 a6 a18 vpp vcc vss a8 a11 a3 a5 a17 rst# clk a20 a9 a12 a2 a7 we# adv# a19 a10 a13 a1 a14 wp# dq12 a16 wait a15 a0 ce# dq1 dq2 dq4 dq6 dq15 vccq oe# dq0 dq9 dq10 dq11 dq13 dq14 vss vssq dq8 vccq dq3 vcc dq5 vssq dq7 a22 a21
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 19 figure 5. 88-ball (80 active balls) quad+ ballout notes: 1. unused upper address balls can be treated as nc (for 128-mbit device, a[25:23] are not used). 2. see section 3.0, ?package information? on page 15 for the mechanical specifications for the package. flash specific sram/psram specific global legend: top view - ball side down 8 7 6 5 4 3 2 1 a b c d e f g h j k l m du a4 du du du du du du du a5 a3 a2 a7 a1 a6 a0 a18 a19 vss vss a23 a24 a25 a17 f2-vcc clk a21 a22 a12 a11 a13 a9 p1-cs# f-vpp, f-vpen a20 a10 a15 f-we# a8 d8 d2 d10 d5 d13 wait a14 a16 f1-ce# p-mode, p-cre vss vss vss p2-cs# f1-vcc f2-vcc vccq f3-ce# d0 d1 d9 d3 d4 d6 d7 d15 d11 d12 d14 f1-oe# f2-oe# p-vcc s-cs2 r-we# r-ub# r-lb# r-oe# s-vcc s-cs1# f1-vcc f-wp# adv# f-rst# f2-ce# vccq vss vss vccq vss
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 20 order number: 290701, revision: 015 4.2 signal descriptions table 5 describes the signals used on the vf bga package. table 6 describes the signals used on the quad+ package. table 5. signal descriptions - vf bga package symbol type name and function a[22:0] input address inputs: for memory addresses. 32-mbit: a[20:0]; 64-mbit: a[21:0]; 128-mbit: a[22:0] d[15:0] input/ output data inputs/outputs: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and configuration code reads. data pins float when the chip or outputs are deselected. data is internally latched during writes. adv# input address valid: adv# indicates valid address presence on address inputs. during synchronous read operations, all addresses are latched on adv#?s rising edge or the next valid clk edge with adv# low, whichever occurs first. ce# input chip enable: asserting ce# activates internal control logic, i/o buffers, decoders, and sense amps. de-asserting ce# deselects the device, places it in standby mode, and places all outputs in high-z. clk input clock: clk synchronizes the device to the system bus frequency during synchronous reads and increments an internal address generator. during synchronous read operations, addresses are latched on adv#?s rising edge or the next valid clk edge with adv# low, whichever occurs first. oe# input output enable: when asserted, oe# enables the device?s output data buffers during a read cycle. when oe# is deasserted, data outputs are placed in a high-impedance state. rst# input reset: when low, rst# resets internal automation and inhibits write operations. this provides data protection during power transitions. de-asserting rst# enables normal operation and places the device in asynchronous read-array mode. wait output wait: the wait signal indicates valid data during synchronous read modes. it can be configured to be asserted-high or asserted-low based on bit 10 of the read configuration register. wait is tri- stated if ce# is deasserted. wait is not gated by oe#. we# input write enable: we# controls writes to the cui and array. addresses and data are latched on the rising edge of we#. wp# input write protect: disables/enables the lock-down function. when wp# is asserted, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. see section 13.1, ?block lock operations? on page 77 for details on block locking. vpp power erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v cc for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v pp1 min. v pp must remain above v pp1 min to perform in-system flash modification. vpp may be 0 v during read operations. v pp2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. vpp can be connected to 12 v for a cumulative total not to exceed 80 hours. extended use of this pin at 12 v may reduce block cycling capability. vcc power device power supply: writes are inhibited at v cc v lko . device operations at invalid v cc voltages should not be attempted. vccq power output power supply: enables all outputs to be driven at v ccq . this input may be tied directly to vcc. vss power ground: pins for all internal device circuitry must be connected to system ground. vssq power output ground : provides ground to all outputs which are driven by vccq. this signal may be tied directly to vss. du ? do not use: do not use this pin. this pin should not be connected to any power supplies, signals or other pins and must be floated. nc ? no connect: no internal connection; can be driven or floated.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 21 table 6. signal descriptions - quad+ package (sheet 1 of 3) symbol type description a[max:min] input address inputs: inputs for all die addresses during read and write operations. ? 256-mbit die : amax= a23 ? 128-mbit die : amax = a22 ? 64-mbit die : amax = a21 ? 32-mbit die : amax = a20 ? 8-mbit die : amax = a18 a0 is the lowest-order 16-bit wide address. a[25:24] denote high-order addresses reserved for future device densities. d[15:0] input/ output data inputs/outputs: inputs data and commands during write cycles, outputs data during read cycles. data signals float when the device or its outputs are deselected. data are internally latched during writes on the flash device. f[3:1]-ce# input flash chip enable: low-true input. f[3:1]-ce# low selects the associated flash memory die. when asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. f1-ce# selects or deselects flash die #1; f2-ce# selects or deselects flash die #2 and is rfu on combinations with only one flash die. f3-ce# selects or deselects flash die #3 and is rfu on stacked combinations with only one or two flash dies. s-cs1# s-cs2 input sram chip select: low-true / high-true input (s-cs1# / s-cs2 respectively). when either/both sram chip select signals are asserted, sram internal control logic, input buffers, decoders, and sense amplifiers are active. when either/both sram chip select signals are deasserted, the sram is deselected and its power is reduced to standby levels. s-cs1# and s-cs2 are available on stacked combinations with sram die and are rfu on stacked combinations without sram die. p[2:1]-cs# input psram chip select: low-true input. when asserted, psram internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the psram is deselected and its power is reduced to standby levels. p1-cs# selects psram die #1 and is available only on stacked combinations with psram die. this ball is an rfu on stacked combinations without psram. p2-cs# selects psram die #2 and is available only on stacked combinations with two psram dies. this ball is an rfu on stacked combinations without psram or with a single psram. f[2:1]-oe# input flash output enable: low-true input. fx-oe# low enables the selected flash?s output buffers. f[2:1]-oe# high disables the selected flash?s output buffers, placing them in high-z. f1-oe# controls the outputs of flash die #1; f2-oe# controls the outputs of flash die #2 and flash die #3. f2-oe# is available on stacked combinations with two or three flash die and is rfu on stacked combinations with only one flash die. r-oe# input ram output enable: low-true input. r-oe# low enables the selected ram?s output buffers. r-oe# high disables the ram output buffers, and places the selected ram outputs in high-z. r-oe# is available on stacked combinations with psram or sram die, and is an rfu on flash-only stacked combinations. f-we# input flash write enable: low-true input. f-we# controls writes to the selected flash die. address and data are latched on the rising edge of f- we#. r-we# input ram write enable: low-true input. r-we# controls writes to the selected ram die. r-we# is available on stacked combinations with psram or sram die and is an rfu on flash-only stacked combinations.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 22 order number: 290701, revision: 015 clk input clock: synchronizes the flash die with the system bus clock in synchronous read mode and increments the internal address generator. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, addresses are latched on the rising edge adv#, or are continuously flow- through when adv# is kept asserted. wait output wait: output signal. indicates invalid data during synchronous array or non-array flash reads. read configuration register bit 10 (rcr[10]) determines wait-asserted polarity (high or low). wait is high-z if f-ce# is deasserted; wait is not gated by f-oe#. ? in synchronous array or non-array flash read modes, wait indicates invalid data when asserted and valid data when deasserted. ? in asynchronous flash page read, and all flash write modes, wait is asserted. f-wp# input flash write protect: low-true input. f-wp# enables/disables the lock-down protection mechanism of the selected flash die. ? f-wp# low enables the lock-down mechanism where locked down blocks cannot be unlocked with software commands. ? f-wp# high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. adv# input address valid: low-true input. during synchronous flash read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous flash read operations, addresses are latched on the rising edge of adv#, or are continuously flow-through when adv# is kept asserted. r-ub# r-lb# input ram upper / lower byte enables: low-true input. during ram read and write cycles, r-ub# low enables the ram high order bytes on d[15:8], and r- lb# low enables the ram low-order bytes on d[7:0]. r-ub# and r-lb# are available on stacked combinations with psram or sram die and are rfu on flash-only stacked combinations. f-rst# input flash reset: low-true input. f-rst# low initializes flash internal circuitry and disables flash operations. f-rst# high enables flash operation. exit from reset places the flash in asynchronous read array mode. p-mode, p-cre input p-mode (psram mode): low-true input. p-mode is used to program the configuration register, and enter/exit low power mode of psram die. p-mode is available on stacked combinations with asynchronous-only psram die. p-cre (psram configuration register enable): high-true input. p-cre is high, write operations load the refresh control register or bus control register. p-cre is applicable only on combinations with synchronous psram die. p-mode, p-cre is an rfu on stacked combinations without psram die. f-vpp, f-vpen power flash program and erase power: valid f-v pp voltage on this ball enables flash program/ erase operations. flash memory array contents cannot be altered when f-v pp (f-v pen ) < v pplk (v penlk ). erase / program operations at invalid f-v pp (f-v pen ) voltages should not be attempted. refer to flash discrete product datasheet for additional details. f-vpen (erase/program/block lock enables) is not available for l18/l30 scsp products. f[2:1]-vcc power flash logic power: f1-vcc supplies power to the core logic of flash die #1; f2-vcc supplies power to the core logic of flash die #2 and flash die #3. write operations are inhibited when f-v cc < v lko . device operations at invalid f-v cc voltages should not be attempted. f2-vcc is available on stacked combinations with two or three flash dies, and is an rfu on stacked combinations with only one flash die. table 6. signal descriptions - quad+ package (sheet 2 of 3)
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 23 s-vcc power sram power supply: supplies power for sram operations. s-vcc is available on stacked combinations with sram die, and is rfu on stacked combinations without sram die. p-vcc power psram power supply: supplies power for psram operations. p-vcc is available on stacked combinations with psram die, and is rfu on stacked combinations without psram die. vccq power device i/o power: supply power for the device input and output buffers. vss power device ground: connect to system ground. do not float any vss connection. rfu ? reserved for future use: reserved for future device functionality/ enhancements. contact intel regarding the use of balls designated rfu. du ? do not use: do not connect to any other signal, or power supply; must be left floating. table 6. signal descriptions - quad+ package (sheet 3 of 3)
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 24 order number: 290701, revision: 015 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. notice: this datasheet contains information on products in the design phase of development. the information here is subject to change without notice. do not final- ize a design with this information. table 7. absolute maximum ratings parameter maximum rating notes temperature under bias ?40 c to +85 c storage temperature ?65 c to +125 c voltage on any pin (except v cc , v ccq , v pp ) ?0.5 v to +2.45 v 1,2 v pp voltage ?0.2 v to +13.1 v 1,3,4 v cc and v ccq voltage ?0.2 v to +2.45 v 1,2 output short circuit current 100 ma 5 notes: 1. specified voltages are with respect to v ss. 2. during transitions, this level may undershoot to (130 nm) ?2.0 v for periods < 20 ns and overshoot to v ccq +2.0 v for periods < 20 ns (90 nm) ?1.0 v for periods < 20 ns and overshoot to v ccq +1.0 v for periods < 20 ns . 3. maximum dc voltage on v pp may overshoot to +14.6 v for periods < 20 ns. 4. v pp program voltage is normally v pp1 . v pp can be 12 v 0.6 v for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. 5. output shorted for no more than one second. no more than one output shorted at a time.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 25 5.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended, and extended exposure beyond the ?operating conditions? may affect device reliability. table 8. extended temperature operation symbol parameter 1 min nom max unit note t a operating temperature ?40 25 85 c v cc supply voltage 1.7 1.8 1.95 v 3 i/o supply voltage (90 nm) 1.7 1.8 1.95 3 i/o supply voltage (130 nm) 1.70 1.8 2.24 3 extended i/o supply voltage (130 nm) 1.35 1.5 1.8 4 v pp1 v pp voltage supply (logic level) 0.90 1.80 1.95 2 programming v pp 11.4 12.0 12.6 2 t pph maximum v pp hours v pp = 12 v - - 80 hours 2 block erase cycles main and parameter blocks v pp v cc 100,000 - - cycles 2 main blocks v pp = 12 v - - 1000 2 parameter blocks v pp = 12 v - - 2500 2 notes: 1. see section 6.1, ?dc current characteristics? on page 26 and section 6.2, ?dc voltage characteristics? on page 28 for specific voltage-range specifications. 2. vpp is normally v pp1 . vpp can be connected to 11.4 v?12.6 v for 1000 cycles on main blocks at extended temperatures and 2500 cycles on parameter blocks at extended temperatures. 3. contact your intel field representative for v cc /v ccq operations down to 1.65 v. 4. see the tables in section 5.0, ?maximum ratings and operating conditions? on page 24 and in section 7.0, ?ac characteristics? on page 29 for operating characteristics within the extended v ccq voltage range.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 26 order number: 290701, revision: 015 6.0 electrical specifications 6.1 dc current characteristics table 9. dc current characteristics (sheet 1 of 2) symbol parameter (1) v ccq = 1.35 v ? 1.8 v (2) v ccq = 1.8 v unit test condition note 32/64/128- mbit 32/64-mbit 128-mbit typ max typ max typ max i li input load - tbd - 1 - 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd 8 i lo output leakage d[15:0] - tbd - 1 - 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd 130 nm i ccs v cc standby tbdtbd850870 a v cc = v cc max v ccq = v ccq max ce# = v cc rst# =v ccq 9 90 nm i ccs - - 22 50 - - 130 nm i ccaps aps tbdtbd850870 a v cc = v cc max v ccq = v ccq max ce# = v ssq rst# =v ccq all other inputs =v ccq or v ssq 10 90 nm i ccaps - - 22 50 - - i ccr average v cc read asynchronous page mode f=13 mhz tbdtbd3647ma4 word read 3 synchronous clk = 40 mhz tbdtbd613613maburst length = 4 3 tbdtbd814814maburst length = 8 tbd tbd 10 18 11 19 ma burst length =16 tbd tbd 11 20 11 20 ma burst length = continuous synchronous clk = 54 mhz tbdtbd716716maburst length = 4 3 tbd tbd 10 18 10 18 ma burst length = 8 tbd tbd 12 22 12 22 ma burst length = 16 tbd tbd 13 25 13 25 ma burst length = continuous i ccr average v cc read synchronous clk = 66 mhz tbd tbd 8 17 - - ma burst length = 4 3, 4 tbd tbd 11 20 - - ma burst length = 8 tbd tbd 14 25 - - ma burst length = 16 tbd tbd 16 30 - - ma burst length = continuous
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 27 i ccw v cc program tbd tbd 18 40 18 40 ma v pp = v pp1, program in progress 4,5,6 tbd tbd 8 15 8 15 ma v pp = v pp2, program in progress i cce v cc block erase tbd tbd 18 40 18 40 ma v pp = v pp1, block erase in progress 4,5,6 tbd tbd 8 15 8 15 ma v pp = v pp2, block erase in progress 130nm i ccws v cc program suspend tbd tbd 8 50 5 25 a ce# = v cc, program sus- pended 7 90nm i ccws tbd tbd 22 50 - - a 130nm i cces v cc erase suspend tbd tbd 8 50 5 25 a ce# = v cc, erase sus- pended 7 90nm i ccws tbd tbd 22 50 - - a i pps (i ppws, i ppes ) v pp standby v pp program suspend v pp erase suspend tbd tbd 0.2 5 0.2 5 a v pp < v cc 4 i ppr v pp read tbd tbd 2 15 2 15 a v pp v cc i ppw v pp program tbd tbd 0.05 0.10 0.05 0.10 ma v pp = v pp1, program in progress 5 tbd tbd 8 22 16 37 v pp = v pp2, program in progress i ppe v pp erase tbd tbd 0.05 0.10 0.05 0.10 ma v pp = v pp1, erase in progress 5 tbd tbd 8 22 8 22 v pp = v pp2, erase in progress notes: 1. all currents are rms unless noted. typical values at typical v cc , t a = +25 c. 2. v ccq = 1.35 v - 1.8v is available on 130 nm products only. 3. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation. see i ccrq specification for details. 4. sampled, not 100% tested. 5. v cc read + program current is the sum of v cc read and v cc program currents. 6. v cc read + erase current is the sum of v cc read and v cc erase currents. 7. i cces is specified with device deselected. if device is read while in erase suspend, current is i cces plus i ccr . 8. if v in >v cc the input load current increases to 10 a max. 9. i ccs is the average current measured over any 5 ms time interval 5 s after a ce# de-assertion. 10. refer to section section 8.2, ?automatic power savings (aps)? on page 51 for i ccaps measurement details. table 9. dc current characteristics (sheet 2 of 2) symbol parameter (1) v ccq = 1.35 v ? 1.8 v (2) v ccq = 1.8 v unit test condition note 32/64/128- mbit 32/64-mbit 128-mbit typ max typ max typ max
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 28 order number: 290701, revision: 015 6.2 dc voltage characteristics table 10. dc voltage characteristics symbol parameter v ccq = 1.35 v ? 1.8 v (1) v ccq = 1.8 v unit test condition note 32/64/128-mbit 32/64-mbit 128-mbit min max min max min max v il input low 0 0.2 0 0.4 0 0.4 v 2 v ih input high v ccq ? 0.2 v ccq v ccq ? 0.4 v ccq v ccq ? 0.4 v ccq v2 v ol output low - 0.1 - 0.1 - 0.1 v v cc = v cc min v ccq = v ccq min i ol = 100 a v oh output high v ccq ? 0.1 - v ccq ? 0.1 - v ccq ? 0.1 -v v cc = v cc min v ccq = v ccq min i oh = ?100 a v pplk v pp lock-out - 0.4 - 0.4 - 0.4 v 3 v lko v cc lock (130nm) 1.0 - 1.0 - 1.0 - v 4 v cc lock (90nm) 0.7 - 0.7 - - - v v ilkoq v ccq lock tbd - 0.9 - 0.9 - v notes: 1. v ccq = 1.35 v - 1.8v is available on 130 nm devices only. 2. v il can undershoot to ?1.0 v for durations of 2 ns or less and v ih can overshoot to v ccq +1.0 v for durations of 2 ns or less. 3. v pp < = v pplk inhibits erase and program operations. don?t use v ppl and v pph outside their valid ranges. 4. block erases, programming and lock-bit configurations are inhibited when v cc intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 29 7.0 ac characteristics table 11. read operations - 90 nm lithography (sheet 1 of 2) # symbol parameter (1,2) v ccq = 1.70 v ? 1.95 v unit notes min max asynchronous specifications r1 t avav read cycle time 60 - ns 7,8 r2 t avqv address to output valid - 60 ns 7,8 r3 t elqv ce# low to output valid - 60 ns 7,8 r4 t glqv oe# low to output valid - 20 ns 4 r5 t phqv rst# high to output valid - 150 ns r6 t elqx ce# low to output low-z 0 - ns 5 r7 t glqx oe# low to output low-z 0 - ns 4,5 r8 t ehqz ce# high to output high-z - 14 ns 5 r9 t ghqz oe# high to output high-z - 14 ns 4,5 r10 t oh ce# (oe#) high to output low-z 0 - ns 4,5 r11 t ehel ce# pulse width high 14 - ns 6 r12 t eltv ce# low to wait valid - 11 ns 6 r13 t ehtz ce# high to wait high-z - 11 ns 5,6 latching specifications r101 t avvh address setup to adv# high 7 - ns r102 t elvh ce# low to adv# high 10 - ns r103 t vlqv adv# low to output valid - 60 ns 7,8 r104 t vlvh adv# pulse width low 7 - ns r105 t vhvl adv# pulse width high 7 - ns r106 t vhax address hold from adv# high 7 - ns 3 r108 t apa page address access time - 20 ns clock specifications r200 f clk clk frequency - 66 mhz r201 t clk clk period 15 - ns r202 t ch/l clk high or low time 3.5 - ns r203 t chcl clk fall or rise time - 3 ns
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 30 order number: 290701, revision: 015 1. see figure 20, ?ac input/output reference waveform? on page 49 for timing measurements and maximum allowable input slew rate. 2. ac specifications assume the data bus voltage is less than or equal to v ccq when a read operation is initiated. 3. address hold in synchronous-burst mode is defined as t chax or t vhax , whichever timing specification is satisfied first. 4. oe# may be delayed by up to t elqv ? t glqv after the falling edge of ce# without impact to t elqv . 5. sampled, not 100% tested. 6. applies only to subsequent synchronous reads. 7. during the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data bus as early as the first clock edge after t avqv . 8. all the preceding specifications apply to all densities. synchronous specifications r301 t avch address valid setup to clk 7 - ns r302 t vlch adv# low setup to clk 7 - ns r303 t elch ce# low setup to clk 7 - ns r304 t chqv clk to output valid - 11 ns 8 r305 t chqx output hold from clk 3 - ns r306 t chax address hold from clk 7 - ns 3 r307 t chtv clk to wait valid - 11 ns 8 table 11. read operations - 90 nm lithography (sheet 2 of 2) # symbol parameter (1,2) v ccq = 1.70 v ? 1.95 v unit notes min max
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 31 table 12. read operations - 130 nm lithography (sheet 1 of 2) # symbol parameter (1,2) v ccq = 1.35 v ? 1.8 v v ccq = 1.70 v ? 2.24 v unit notes -65 -85 -60 -80 min max min max min max min max asynchronous specifications r1 t avav read cycle time 65 - 85 - 60 - 80 - ns 7,8 r2 t avqv address to output valid - 65 - 85 - 60 - 80 ns 7,8 r3 t elqv ce# low to output valid - 65 - 85 - 60 - 80 ns 7,8 r4 t glqv oe# low to output valid - 25 - 30 - 20 - 25 ns 4 r5 t phqv rst# high to output valid - 150 - 150 - 150 - 150 ns r6 t elqx ce# low to output low-z 0 - 0 0 - 0 ns 5 r7 t glqx oe# low to output low-z 0 - 0 0 - 0 - ns 4,5 r8 t ehqz ce# high to output high-z - 17 - 20 - 14 - 17 ns 5 r9 t ghqz oe# high to output high-z - 14 - 14 - 14 - 14 ns 4,5 r10 t oh ce# (oe#) high to output low-z 0 - 0 0 - 0 - ns 4,5 r11 t ehel ce# pulse width high - 14 - 14 - 14 - 14 ns 6 r12 t eltv ce# low to wait valid - 14 - 20 - 11 - 14 ns 5,6 r13 t ehtz ce# high to wait high-z 14 - 20 - 14 - 14 - ns 6 latching specifications r101 t avvh address setup to adv# high 7 - 7 - 7 - 7 - ns r102 t elvh ce# low to adv# high 10 - 10 - 10 - 10 - ns r103 t vlqv adv# low to output valid - 65 - 85 - 60 - 80 ns 7,8 r104 t vlvh adv# pulse width low 7 - 7 - 7 - 7 - ns r105 t vhvl adv# pulse width high 7 - 7 - 7 - 7 - ns r106 t vhax address hold from adv# high 7 - 7 - 7 - 7 - ns 3 r108 t apa page address access time - 25 - 30 - 20 - 25 ns clock specifications r200 f clk clk frequency - 54 - 40 - 66 - 54 mhz r201 t clk clk period 18.5 - 25 - 15 - 18.5 - ns r202 t ch/l clk high or low time 4.5 - 9.5 - 3.5 - 4.5 - ns r203 t chcl clk fall or rise time -3-3-3-3ns
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 32 order number: 290701, revision: 015 note: for all numbered note references in this table, refer to the notes in table 11, ?read operations - 90 nm lithography? on page 29 . synchronous specifications r301 t avch address valid setup to clk 7 - 7 - 7 - 7 - ns r302 t vlch adv# low setup to clk 7 - 7 - 7 - 7 - ns r303 t elch ce# low setup to clk 7 - 7 - 7 - 7 - ns r304 t chqv clk to output valid - 14 - 20 - 11 - 14 ns 8 r305 t chqx output hold from clk 3 - 3 - 3 - 3 - ns r306 t chax address hold from clk 7 - 7 - 7 - 7 - ns 3 r307 t chtv clk to wait valid - 14 - 20 - 11 - 14 ns 8 table 12. read operations - 130 nm lithography (sheet 2 of 2) # symbol parameter (1,2) v ccq = 1.35 v ? 1.8 v v ccq = 1.70 v ? 2.24 v unit notes -65 -85 -60 -80 minmaxminmaxminmaxminmax
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 33 notes: 1. wait shown asserted (rcr[10]=0) 2. adv# assumed to be driven to vil in this waveform figure 6. asynchronous read operation waveform v ih v il valid address v ih v il v ih v il v ih v il high z v oh v ol valid output v ih v il r1 r2 r3 r4 r5 r7 r10 address [a] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] r8 r9 v oh v ol high z wait [t] high z note 1
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 34 order number: 290701, revision: 015 figure 7. latched asynchronous read operation waveform v oh v ol high z valid output v ih v il v ih v il v ih v il valid address v ih v il v ih v il v ih v il data [q] we# [w] oe# [g] ce# [e] a[max:2] [a] adv# [v] rst# [p] r102 r104 r1 r2 r3 r4 r5 r6 r7 r10 r103 r101 r105 r106 a[1:0] [a] v ih v il valid address valid address valid address r8 r9
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 35 note: wait shown asserted (rcr[10] = 0). figure 8. page-mode read operation waveform r105 v ih v il v ih v il v ih v il v ih v il v oh v ol high z valid output valid output valid output valid output v ih v il v ih v il valid address v ih v il valid address valid address valid address valid address r102 r104 adv# [v] ce# [e] oe# [g] we# [w] data [d/q] rst# [p] a[max:2] [a] a[1:0] [a] r1 r2 r101 r106 r103 r3 r4 r7 r6 r108 r10 r5 r9 r8 v oh v ol high z wait [t] high z note 1
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 36 order number: 290701, revision: 015 notes: 1. section 14.2, ?first access latency count (rcr[13:11])? on page 86 describes how to insert clock cycles during the initial access. 2. wait (shown asserted; rcr[10]=0) can be configured to assert either during, or one data cycle before, valid data. 3. this waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a ce# de- assertion after the first word in the burst. if this access had been done to status, id, or query reads, the asserted (low) wait signal would have remained asserted (low) as long as ce# is asserted (low). figure 9. single synchronous read-array operation waveform r12 r13
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 37 notes: 1. section 14.2, ?first access latency count (rcr[13:11])? on page 86 describes how to insert clock cycles during the initial access. 2. wait (shown asserted; rcr[10] = 0) can be configured to assert either during, or one data cycle before, valid data. figure 10. synchronous 4-word burst read operation waveform r12 r11 r13
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 38 order number: 290701, revision: 015 notes: 1. section 14.2, ?first access latency count (rcr[13:11])? on page 86 describes how to insert clock cycles during the initial access. 2. wait (shown asserted; rcr[10]=0) can be configured to assert either during, or one data cycle before, valid data (assumed wait delay of two clocks, for example). figure 11. wait functionality for eowl (end-of-word line) condition waveform r12
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 39 notes: 1. section 14.2, ?first access latency count (rcr[13:11])? on page 86 describes how to insert clock cycles during the initial access. 2. wait shown asserted (rcr[10]=0). figure 12. wait signal in synchronous non-read array operation waveform r12 r13
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 40 order number: 290701, revision: 015 note: during burst suspend, clock signal can be held high or low. figure 13. burst suspend q0 q1 q1 q2 r304 r304 r7 r6 r13 r12 r9 r4 r9 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 r305 r305 r305 r304 clk address [a] adv# ce# [e] oe# [g] wait [t] we# [w] d ata [d/q]
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 41 7.1 ac write characteristics table 13. ac write characteristics - 90 nm lithography # sym parameter (1,2) v ccq = 1.70 v ? 1.95 v unit notes min max w1 t phwl (t phel ) rst# high recovery to we# (ce#) low 150 - ns 3 w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) low 0 - ns w3 t wlwh (t eleh ) we# (ce#) write pulse width low 40 - ns 4 w4 t dvwh (t dveh ) data setup to we# (ce#) high 40 - ns w5 t avwh (t aveh ) address setup to we# (ce#) high 40 - ns w6 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 - ns w7 t whdx (t ehdx ) data hold from we# (ce#) high 0 - ns w8 t whax (t ehax ) address hold from we# (ce#) high 0 - ns w9 t whwl (t ehel ) we# (ce#) pulse width high 20 - ns 5,6,7 w10 t vpwh (t vpeh ) vpp setup to we# (ce#) high 200 - ns 3 w11 t qvvl vpp hold from valid srd 0 - ns 3,8 w12 t qvbl wp# hold from valid srd 0 - ns 3,8 w13 t bhwh (t bheh ) wp# setup to we# (ce#) high 200 - ns 3 w14 t whgl (t ehgl ) write recovery before read 0 - ns w16 t whqv we# high to valid data t avqv +20 -ns3,6,10 w18 t whav we# high to address valid 0 - ns 3,9,10 w19 t whcv we# high to clk valid 12 - ns 3,10 w20 t whvh we# high to adv# high 12 - ns 3,10 w21 t vhwl adv# high to we# low < 21 ns 11 w22 t chwl clk to we# low < 21 ns 11 w27 t whel we# high to ce# low 0 w28 t whvl we# high to adv# low 0 notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever is first) to ce# or we# low (whichever is last). hence, t wlwh = t ehel = t whel = t ehwl . 6. system designers should take this into account and may insert a software no-op instruction to delay the first read after issuing a command. 7. for commands other than resume commands. 8. vpp should be held at vpp1 or vpp2 until block erase or program success is determined. 9. applicable during asynchronous reads following a write. 10. t whch/l or t whvh must be met when transitioning from a write cycle to a synchronous burst read. t whch/l and t whvh both refer to the address latching event (either the rising/falling clock edge or the rising adv# edge, whichever occurs first). 11. the specifications t vhwl and t chwl can be ignored if there is no clock toggling during the write bus cycle.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 42 order number: 290701, revision: 015 table 14. ac write characteristics - 130 nm lithography # sym parameter (1,2) v ccq = 1.35 v ? 1.8 v v ccq = 1.70 v ? 2.24 v unit notes -65 -85 -60 -80 min max min max min max min max w1 t phwl (t phel ) rst# high recovery to we# (ce#) low 150 - 150 - 150 - 150 - ns 3 w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) low 0-0-0-0-ns w3 t wlwh (t eleh ) we# (ce#) write pulse width low 50 - 60 - 40 - 60 - ns 4 w4 t dvwh (t dveh ) data setup to we# (ce#) high 50 - 60 - 40 - 60 - ns w5 t avwh (t aveh ) address setup to we# (ce#) high 50 - 60 - 40 - 60 - ns w6 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0-0-0-0-ns w7 t whdx (t ehdx ) data hold from we# (ce#) high 0 - 0 - 0 - 0 - ns w8 t whax (t ehax ) address hold from we# (ce#) high 0-0-0-0-ns w9 t whwl (t ehel ) we# (ce#) pulse width high 20 - 25 - 20 - 25 - ns 5,6,7 w10 t vpwh (t vpeh ) vpp setup to we# (ce#) high 200 - 200 - 200 - 200 - ns 3 w11 t qvvl vpp hold from valid srd 0 - 0 - 0 - 0 - ns 3,8 w12 t qvbl wp# hold from valid srd 0-0-0-0-ns3,8 w13 t bhwh (t bheh ) wp# setup to we# (ce#) high 200 - 200 - 200 - 200 - ns 3 w14 t whgl (t ehgl )write recovery before read 0-0-0-0-ns w16 t whqv we# high to valid data t avqv + 25 - t avqv + 55 - t avqv +20 - t avqv +50 - ns 3,6,10 w18 t whav we# high to address valid 0-0-0-0-ns3,9,10 w19 t whcv we# high to clk valid 16 - 20 - 12 - 20 - ns 3,10 w20 t whvh we# high to adv# high 16 - 20 - 12 - 20 - ns 3,10 notes: for all numbered note references in this table, refer to the notes in table 13, ?ac write characteristics - 90 nm lithography? on page 41 .
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 43 notes: 1. v cc power-up and standby. 2. write program or erase setup command. 3. write valid address and data (for program) or erase confirm command. 4. automated program/erase delay. 5. read status register data (srd) to determine program/erase operation completion. 6. oe# and ce# must be asserted and we# must be deasserted for read operations. 7. clk is ignored. (but may be kept active/toggling) figure 14. write operations waveform note 1 note 2 note 3 note 4 note 5 address [a] v ih v il valid address valid address ce# (we#) [e(w)] v ih v il note 6 oe# [g] v ih v il we# (ce#) [w(e)] v ih v il rst# [p] v ih v il w6 w7 w8 w11 w12 r105 vpp [v] v pph v pplk v il wp# [b] v ih v il data [q] v ih v il data in valid srd adv# [v] v ih v il w16 w1 w2 w3 w4 w9 w10 w13 w14 r101 r106 data in valid address note 6 r104 w5 w18 w19 w20 clk [c] v ih v il
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 44 order number: 290701, revision: 015 figure 15. asynchronous read to write operation waveform figure 16. asynchronous write to read operation q d r5 w7 w4 r10 r7 r6 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a ddress [a] ce# [e} oe# [g] we# [w] data [d/q] rst# [p] d q w1 r 9 r8 r4 r3 r2 w7 w4 w1 4 w18 w3 w3 r10 w6 w2 r1 r1 w8 w5 a d d re ss [ a ] ce# [e} we# [w] oe# [g] data [d/q] rst # [p]
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 45 figure 17. synchronous read to write operation latency count q d d w7 r13 r305 r304 r7 r307 r12 w1 5 w9 w19 w8 w9 w3 w3 w2 r8 r4 w6 r11 r11 r303 r3 w2 0 r104 r104 r106 r102 r105 r105 w1 8 w5 r101 r2 r306 r302 r301 clk [c] a ddress [a] ad v# [v] ce# [e] oe# [g] we# wait [t] d ata [d /q]
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 46 order number: 290701, revision: 015 figure 18. synchronous write to read operation lat ency count d q q w1 r304 r305 r304 r3 w7 w4 r307 r12 r4 w18 w19 w3 w3 r11 r303 r11 w6 w2 w20 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk a ddres s [a ] adv# ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst# [p]
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 47 7.2 erase and program times table 15. erase and program times operation symbol parameter description (1) notes v pp1 v pp2 unit typ max typ max erasing and suspending erase time w500 ters/pb 4-kword parameter block 2,3 0.3 2.5 0.25 2.5 s w501 t ers/mb 32-kword main block 2,3 0.7 4 0.4 4 s suspend latency w600 t susp/p program suspend 2 5 10 5 10 s w601 t susp/e erase suspend 2 5 20 5 20 s programming program time w200 tprog/w single word 2 12 150 8 130 s w201 tprog/pb 4-kword parameter block 2,3 0.05 .23 0.03 0.07 s w202 tprog/mb 32-kword main block 2,3 0.4 1.8 0.24 0.6 s enhanced factory programming (5) program w400 tefp/w single word 4 n/a n/a 3.1 16 s w401 tefp/pb 4-kword parameter block 2,3 n/a - 15 - ms w402 tefp/mb 32-kword main block 2,3 n/a - 120 - ms operation latency w403 t efp/setup efp setup - n/a - 5 s w404 t efp/tran program to verify transition n/a n/a 2.7 5.6 s w405 t efp/verify verify n/a n/a 1.7 130 s notes: 1. unless noted otherwise, all parameters are measured at t a = +25 c and nominal voltages, and they are sampled, not 100% tested. 2. excludes external system-level overhead. 3. exact results may vary based on system overhead. 4. w400-typ is the calculated delay for a single programming pulse. w400-max includes the delay when programming within a new word-line. 5. some efp performance degradation may occur if block cycling exceeds 10.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 48 order number: 290701, revision: 015 7.3 reset specifications table 16. reset specifications # symbol parameter (1) notes min max unit p1 t plph rst# low to reset during read 1, 2, 3, 4 100 - ns p2 t plrh rst# to 1, 3, 4, 5 - s rst# to reset during 1, 3, 4, 5 - s p3 t vccph vcc power valid to reset 1,3,4,5,6 60 - s notes: 1. these specifications are valid for all product versions (packages and speeds). 2. the device may reset if t plph < t plph min, but this is not guaranteed. 3. not applicable if rst# is tied to vcc. 4. sampled, but not 100% tested. 5. if rst# is tied to vcc, the device is not ready until t vccph occurs after when v cc v cc min. 6. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc v cc min. figure 19. reset operations waveforms ( a) reset during read mode ( b) reset during program or block erase p1 p2 ( c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v vcc ( d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 49 7.4 ac i/o test conditions note: input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed conditions are when v cc = v cc min. note: see table 16 on page 48 for component values. figure 20. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input outpu t figure 21. transient equivalent testing load circuit device under test v ccq c l r 2 r 1 out table 17. test configuration component values for worst case speed conditions test configuration c l (pf) r 1 (k )r 2 (k ) -- 30 13.5 13.5 -- 30 16.7 16.7 note: c l includes jig capacitance. figure 22. clock input ac waveform clk [c] v ih v il r203 r202 r201
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 50 order number: 290701, revision: 015 7.5 device capacitance t a = +25 c, f = 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v c ce ce# input capacitance 10 12 pf v in = 0.0 v sampled, not 100% tested.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 51 8.0 power and reset specifications intel ? wireless flash memory (w18) devices have a layered approach to power savings that can significantly reduce overall system power consumption. the aps feature reduces power consumption when the device is selected but idle. if ce# is deasserted, the memory enters its standby mode, where current consumption is even lower. asserting rst# provides current savings similar to standby mode. the combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 8.1 active power with ce# at v il and rst# at v ih , the device is in the active mode. refer to section 6.1, ?dc current characteristics? on page 26 , for i cc values. when the device is in ?active? state, it consumes the most power from the system. minimizing device active current therefore reduces system power consumption, especially in battery-powered applications. 8.2 automatic power savings (aps) automatic power saving (aps) provides low - power operation during a read?s active state. during aps mode, i ccaps is the average current measured over any 5 ms time interval 5 s after the following events happen: ? there is no internal sense activity; ? ce# is asserted; ? the address lines are quiescent, and at v ssq or v ccq . oe# may be asserted during aps. 8.3 standby power with ce# at v ih and the device in read mode, the flash memory is in standby mode, which disables most device circuitry and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the oe# signal state. if ce# transitions to v ih during erase or program operations, the device continues the operation and consumes corresponding active power until the operation is complete. i ccs is the average current measured over any 5 ms time interval 5 s after a ce# de-assertion. 8.4 power-up/down characteristics the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required if v cc , v ccq , and v pp are connected together; so it doesn?t matter whether v pp or v cc powers-up first. if v ccq and/or v pp are not connected to the system supply, then v cc should attain v ccmin before applying vccq and vpp. device inputs should not be driven before supply voltage = v ccmin. power supply transitions should only occur when rst# is low.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 52 order number: 290701, revision: 015 8.4.1 system reset and rst# the use of rst# during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. to allow proper cpu/flash initialization at system reset, connect rst# to the system cpu reset# signal. system designers must guard against spurious writes when vcc voltages are above v lko . because both we# and ce# must be low for a command write, driving either signal to v ih inhibits writes to the device. the cui architecture provides additional protection because alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until rst# is brought to v ih , regardless of its control input states. by holding the device in reset (rst# connected to system powergood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 8.4.2 vcc, vpp, and rst# transitions the cui latches commands issued by system software and is not altered by vpp or ce# transitions or wsm actions. read-array mode is its power-up default state after exit from reset mode or after vcc transitions above v lko (lockout voltage). after completing program or block erase operations (even after vpp transitions below v pplk ), the read array command must reset the cui to read-array mode if flash memory array access is desired. 8.5 power supply decoupling when the device is accessed, many internal conditions change. circuits are enabled to charge pumps and switch voltages. this internal activity produces transient noise. to minimize the effect of this transient noise, device decoupling capacitors are required. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each power (vcc, vccq, vpp) , and ground (vss, vssq) signal. high-frequency, inherently low-inductance capacitors should be as close as possible to package signals.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 53 9.0 bus operations overview this section provides an overview of device bus operations. the intel ? wireless flash memory (w18) family includes an on-chip wsm to manage block erase and program algorithms. its command user interface (cui) allows minimal processor overhead with ram-like interface timings. device commands are written to the cui using standard microprocessor timings. 9.1 bus operations bus cycles to/from the w18 device conform to standard microprocessor bus operations. table 18 summarizes the bus operations and the logic levels that must be applied to the device?s control signal inputs. 9.1.1 reads device read operations are performed by placing the desired address on a[22:0] and asserting ce# and oe#. adv# must be low, and we# and rst# must be high. all read operations are independent of the voltage level on v pp . ce#-low selects the device and enables its internal circuits. oe#-low or we#-low determine whether dq[15:0] are outputs or inputs, respectively. oe# and we# must not be low at the same time - indeterminate device operation will result. in asynchronous-page mode, the risi ng edge of adv# can be used to latch the address. if only asynchronous read mode is used, adv# can be ti ed to ground. clk is not used in asynchronous- page mode and should be tied high. in synchronous-burst mode, adv# is used to latch the initial address - either on the rising edge of adv# or the rising (or falling) edge of clk with adv# low, whichever occurs first. clk is used in synchronous-burst mode to increment the internal address counter, and to output read data on dq[15:0]. each device partition can be placed in any of several read states: table 18. bus operations summary bus operation rst# clk adv# ce# oe# we# wait dq[15:0] notes read asynchronous v ih x l l l h asserted output synchronous v ih running l l l h driven output 1 burst suspend v ih halted x l h h active output write v ih x l l h l asserted input 2 output disable v ih x x l h h asserted high-z 3 standby v ih x x h x x high-z high-z 3 reset v il x x x x x high-z high-z 3,4 notes: 1. wait is only valid during synchronous array-read operations. 2. refer to the table 20, ?bus cycle definitions? on page 58 for valid dq[15:0] during a write operation. 3. x = don?t care (h or l). 4. rst# must be at v ss 0.2 v to meet the maximum specified power-down current.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 54 order number: 290701, revision: 015 ? read array: returns flash array data from the addressed location. ? read identifier (id): returns manufacturer id and device id codes, block lock status, and protection register data. read identifier information can be accessed from any 4-mbit partition base address. ? cfi query: returns common flash interface (cfi) information. cfi information can be accessed starting at 4-mbit partition base addresses. ? read status register: returns status register (sr) data from the addressed partition. the appropriate cui command must be written to the partition in order to place it in the desired read state (see table 19, ?command codes and descriptions? on page 56 ). non-array read operations (read id, cfi query, and read status register) execute as single synchronous or asynchronous read cycles. wait is asserted throughout non-array read operations. 9.1.2 writes device write operations are performed by placing the desired address on a[22:0] and asserting ce# and we#. oe# and rst# must be high. data to be written at the desired address is placed on dq[15:0]. adv# must be held low throughout the write cycle or it can be toggled to latch the address. if adv# is held low, the address and data are latched on the rising edge of we#. clk is not used during write operations, and is ignored; it can be either free-running or halted at v il or v ih . all write operations are asynchronous. table 19, ?command codes and descriptions? on page 56 shows the available device commands. appendix a, ?write state machine states? on page 93 provides information on moving between different device operations by using cui commands. 9.1.3 output disable when oe# is deasserted, device outputs dq[15:0] are disabled and placed in a high - impedance (high-z) state. 9.1.4 burst suspend the burst suspend feature allows the system to temporarily suspend a synchronous-burst read operation. this can be useful if the system needs to access another device on the same address and data bus as the flash during a burst-read operation. synchronous-burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. when a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. burst suspend occurs when ce# is asserted, the current address has been latched (either adv# rising edge or valid clk edge), clk is halted, and oe# is deasserted. clk can be halted when it is at v ih or v il . to resume the burst access, oe# is reasserted and clk is restarted. subsequent clk edges resume the burst sequence where it left off. within the device, ce# gates wait. therefore, during burst suspend wait is still driven. this can cause contention with another device attempting to control the system?s ready signal during a burst suspend. systems using the burst suspend feature should not connect the device?s wait signal directly to the system?s ready signal. refer to figure 13, ?burst suspend? on page 40 .
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 55 9.1.5 standby de-asserting ce# deselects the device and places it in standby mode, substantially reducing device power consumption. in standby mode, outputs are placed in a high-impedance state independent of oe#. if deselected during a program or erase algorithm, the device shall consume active power until the program or erase operation completes. 9.1.6 reset the device enters a reset mode when rst# is asserted. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. after returning from reset, a time t phqv is required until outputs are valid, and a delay (t phwv ) is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. the device defaults to read-array mode, the status register is set to 80h, and the configuration register defaults to asynchronous page-mode reads. if rst# is asserted during an erase or program operation, the operation aborts and the memory contents at the aborted block or address are invalid. see figure 19, ?reset operations waveforms? on page 48 for detailed information regarding reset timings. like any automated device, it is important to assert rst# during system reset. when the system comes out of reset, the processor expects to read from the flash memory array. automated flash memories provide status information when read during program or erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intel flash memories allow proper cpu initialization following a system reset through the use of the rst# input. in this application, rst# is controlled by the same cpu reset signal. 9.2 device commands the device?s on-chip wsm manages erase and program algorithms. this local cpu (wsm) controls the device?s in-system read, program, and erase operations. bus cycles to or from the flash memory conform to standard microprocessor bus cycles. rst#, ce#, oe#, we#, and adv# control signals dictate data flow into and out of the device. wait informs the cpu of valid data during burst reads. table 18, ?bus operations summary? on page 53 summarizes bus operations. device operations are selected by writing specific commands into the device?s cui. table 19, ?command codes and descriptions? on page 56 lists all possible command codes and descriptions. table 20, ?bus cycle definitions? on page 58 lists command definitions. because commands are partition-specific, it is important to issue write commands within the target address range.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 56 order number: 290701, revision: 015 table 19. command codes and descriptions (sheet 1 of 2) operation code device command description read ffh read array places selected partition in read array mode. 70h read status register places selected partition in status register read mode. after issuing this command, reading from the partition outputs sr data on dq[15:0]. a partition automatically enters this mode after issuing the program or erase command. 90h read identifier places the selected partition in read id mode. device reads from partition addresses output manufacturer/device codes, configuration register data, block lock status, or protection register data on dq[15:0]. 98h cfi query puts the addressed partition in cfi query mode. device reads from the partition addresses output cfi information on dq[7:0]. 50h clear status register the wsm can set the status register?s block lock (sr[1]), v pp (sr[3]), program (sr[4]), and erase (sr[5]) status bits, but it cannot clear them. sr[5:3,1] can only be cleared by a device reset or through the clear status register command. program 40h word program setup this preferred program command?s first cycle prepares the cui for a program operation. the second cycle latches address and data, and executes the wsm program algorithm at this location. status register updates occur when ce# or oe# is toggled. a read array command is required to read array data after programming. 10h alternate setup equivalent to a program setup command (40h). 30h efp setup this program command activates efp mode. the first write cycle sets up the command. if the second cycle is an efp confirm command (d0h), subsequent writes provide program data. all other commands are ignored after efp mode begins. d0h efp confirm if the first command was efp setup (30h), the cui latches the address and data, and prepares the device for efp mode. erase 20h erase setup this command prepares the cui for block erase. the device erases the block addressed by the erase confirm command. if the next command is not erase confirm, the cui sets status register bits sr[5:4] to indicate command sequence error and places the partition in the read status register mode. d0h erase confirm if the first command was erase setup (20h), the cui latches address and data, and erases the block indicated by the erase confirm cycle address. during program or erase, the partition responds only to read status register, program suspend, and erase suspend commands. ce# or oe# toggle updates status register data. suspend b0h program suspend or erase suspend this command, issued at any device address, suspends the currently executing program or erase operation. status register data indicates the operation was successfully suspended if sr[2] (program suspend) or sr[6] (erase suspend) and sr[7] are set. the wsm remains in the suspended state regardless of control signal states (except rst#). d0h suspend resume this command, issued at any device address, resumes the suspended program or erase operation.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 57 block locking 60h lock setup this command prepares the cui lock configuration. if the next command is not lock block, unlock block, or lock-down, the cui sets sr[5:4] to indicate command sequence error. 01h lock block if the previous command was lock setup (60h), the cui locks the addressed block. d0h unlock block if the previous command was lock setup (60h), the cui latches the address and unlocks the addressed block. if previously locked-down, the operation has no effect. 2fh lock-down if the previous command was lock setup (60h), the cui latches the address and locks-down the addressed block. protection c0h protection program setup this command prepares the cui for a protection register program operation. the second cycle latches address and data, and starts the wsm?s protection register program or lock algorithm. toggling ce# or oe# updates the flash status register data. to read array data after programming, issue a read array command. configuration 60h configuration setup this command prepares the cui for device configuration. if set configuration register is not the next command, the cui sets sr[5:4] to indicate command sequence error. 03h set configuration register if the previous command was configuration setup (60h), the cui latches the address and writes the data from a[15:0] into the configuration register. subsequent read operations access array data. note: do not use unassigned commands. intel reserves the right to redefine these codes for future functions. table 19. command codes and descriptions (sheet 2 of 2) operation code device command description
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 58 order number: 290701, revision: 015 table 20. bus cycle definitions operation command bus cycles first bus cycle second bus cycle oper addr 1 data 2,3 oper addr 1 data 2,3 read read array/reset 1writepna ffhread read address array data read identifier 2 write pna 90h read pba+ia ic cfi query 2 write pna 98h read pba+qa qd read status register 2 write pna 70h read pna srd clear status register 1 write xx 50h program and erase block erase 2 write ba 20h write ba d0h word program 2 write wa 40h/10h write wa wd efp > 2 write wa 30h write wa d0h program/erase suspend 1 write xx b0h program/erase resume 1 write xx d0h lock lock block 2 write ba 60h write ba 01h unlock block 2 write ba 60h write ba d0h lock-down block 2 write ba 60h write ba 2fh protection protection program 2 write pa c0h write pa pd lock protection program 2 write lpa c0h write lpa fffdh configuration set configuration register 2 write cd 60h write cd 03h notes: 1. first-cycle command addresses should be the same as the operation?s target address. examples: the first-cycle address for the read identifier command should be the same as the identification code address (ia); the first-cycle address for the word program command should be the same as the word address (wa) to be programmed; the first-cycle address for the erase/program suspend command should be the same as the address within the block to be suspended; etc. xx = any valid address within the device. ia = identification code address. ba = block address. any address within a specific block. lpa = lock protection address is obtained from the cfi (through the cfi query command). the intel wireless flash memory family?s lpa is at 0080h. pa = user programmable 4-word protection address. pna = any address within a specific partition. pba = partition base address. the very first address of a particular partition. qa = cfi code address. wa = word address of memory location to be written. 2. srd = status register data. wd = data to be written at location wa. ic = identifier code data. pd = user programmable 4-word protection data. qd = query code data on dq[7:0]. cd = configuration register code data presented on device addresses a[15:0]. a[max:16] address bits can select any partition . see table 28, ?read configuration register descriptions? on page 84 for configuration register bits descriptions. 3. commands other than those shown above are reserved by intel for future device implementations and should not be used.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 59 9.3 command sequencing when issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur between the two write cycles. the setup phase of a 2-cycle write sequence places the addressed partition into read-status mode, so if the same partition is read before the second ?confirm? write cycle is issued, status register data will be returned. reads from other partitions, however, can return actual array data assuming the addressed partition is already in read-array mode. figure 23 and figure 24 illustrate these two conditions. by contrast, a write bus cycle may not interrupt a 2-cycle write sequence. doing so causes a command sequence error to appear in the status register. figure 25 illustrates a command sequence error. figure 23. normal write and read cycles figure 24. interleaving a 2-cycle write sequence with an array read partition a partition a partition a 20h d0h ffh block erase setup block erase conf irm read array a ddress [a] we# [w] oe# [g] data [q] partition b partition a partition b partition a ffh 20h array data d0h read array erase setup bus read erase conf irm a ddress [a] we# [w] oe# [g] data [q] figure 25. improper command sequencing partition x partition y partition x partition x 20h ffh d0 h sr data address [a] we# [w] oe# [g] data [d/q]
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 60 order number: 290701, revision: 015 10.0 read operations the device supports two read modes - asynchronous page and synchronous burst mode. asynchronous page mode is the default read mode after device power-up or a reset. the read configuration register (rcr) must be configured to enable synchronous burst reads of the flash memory array (see section 14.0, ?set read configuration register? on page 84 ). each partition of the device can be in any of four read states: read array, read identifier, read status or cfi query. upon power-up, or after a reset, all partitions of the device default to the read array state. to change a partition?s read state, the appropriate read command must be written to the device (see section 9.2, ?device commands? on page 55 ). the following sections describe device read modes and read states in detail. 10.1 asynchronous page read mode following a device power-up or reset, asynchronous page mode is the default read mode and all partitions are set to read array. however, to perform array reads after any other device operation (e.g. write operation), the read array command must be issued in order to read from the flash memory array. note: asynchronous page-mode reads can only be performed when read configuration register bit rcr[15] is set (see section 14.0, ?set read configuration register? on page 84 ). to perform an asynchronous page mode read, an address is driven onto a[max:0], and ce#, oe# and adv# are asserted. we# and rst# must be deasserted. wait is asserted during asynchronous page mode. adv# can be driven high to latch the address, or it must be held low throughout the read cycle. clk is not used for asynchronous page-mode reads, and is ignored. if only asynchronous reads are to be performed, clk should be tied to a valid v ih level, wait signal can be floated and adv# must be tied to ground. array data is driven onto dq[15:0] after an initial access time t avqv delay. (see section 7.0, ?ac characteristics? on page 29 ). in asynchronous page mode, four data words are ?sensed? simultaneously from the flash memory array and loaded into an internal page buffer. the buffer word corresponding to the initial address on a[max:0] is driven onto dq[15:0] after the initial access delay. address bits a[max:2] select the 4-word page. address bits a[1:0] determine which word of the 4-word page is output from the data buffer at any given time. 10.2 synchronous burst read mode to perform a synchronous burst- read, an initial address is driven onto a[max:0], and ce# and oe# are asserted. we# and rst# must be deasserted. adv# is asserted, and then deasserted to latch the address. alternately, adv# can remain asserted throughout the burst access, in which case the address is latched on the next valid clk edge after adv# is asserted. see section 14.0, ?set read configuration register? on page 84 during synchronous array and non-array read modes, the first word is output from the data buffer on the next valid clk edge after the initial access latency delay (see section 14.2, ?first access latency count (rcr[13:11])? on page 86 ). subsequent data is output on valid clk edges
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 61 following a minimum delay. however, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. see section 7.0, ?ac characteristics? on page 29 10.3 read array the read array command places (or resets) the partition in read-array mode and is used to read data from the flash memory array. upon initial device power-up, or after reset (rst# transitions from v il to v ih ), all partitions default to asynchronous read-array mode. to read array data from the flash device, first write the read array command (ffh) to the cui and specify the desired word address. then read from that address. if a partition is already in read-array mode, issuing the read array command is not required to read from that partition. if the read array command is written to a partition that is erasing or programming, the device presents invalid data on the bus until the program or erase operation completes. after the program or erase finishes in that partition, valid array data can then be read. if an erase suspend or program suspend command suspends the wsm, a subsequent read array command places the addressed partition in read-array mode. the read array command functions independently of v pp . 10.4 read identifier the read identifier mode outputs the manufacturer/device identifier, block lock status, protection register codes, and configuration register data. the identifier information is contained within a separate memory space on the device and can be accessed along the 4-mbit partition address range supplied by the read identifier command (90h) address. reads from addresses in table 21 retrieve id information. issuing a read identifier command to a partition that is programming or erasing places that partition?s outputs in read id mode while the partition continues to program or erase in the background. table 21. device identification codes (sheet 1 of 2) item address 1 data description base offset manufacturer id partition 00h 0089h intel device id partition 01h 8862h 32-mbit tpd 8863h 32-mbit bpd 8864h 64-mbit tpd 8865h 64-mbit bpd 8866h 128-mbit tpd 8867h 128-mbit bpd block lock status (2) block 02h d0 = 0 block is unlocked d0 = 1 block is locked block lock-down status (2) block 02h d1 = 0 block is not locked-down d1 = 1 block is locked down configuration register partition 05h register data
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 62 order number: 290701, revision: 015 10.5 cfi query this device contains a separate cfi query database that acts as an ?on-chip datasheet.? the cfi information within this device can be accessed by issuing the read query command and supplying a specific address. the address is constructed from the base address of a partition plus a particular offset corresponding to the desired cfi field. appendix b, ?common flash interface (cfi)? on page 96 shows accessible cfi fields and their address offsets. issuing the read query command to a partition that is programming or erasing puts that partition in read query mode while the partition continues to program or erase in the background. 10.6 read status register the device?s status register displays program and erase operation status. a partition?s status can be read after writing the read status register command to any location within the partition?s address range. read-status mode is the default read mode following a program, erase, or lock block command sequence. subsequent single reads from that partition will return its status until another valid command is written. the read-status mode supports single synchronous and single asynchronous reads only; it doesn?t support burst reads. the first falling edge of oe# or ce# latches and updates status register data. the operation doesn?t affect other partitions? modes. because the status register is 8 bits wide, only dq [7:0] contains valid status register data; dq [15:8] contains zeros. see table 22, ?status register definitions? on page 63 and table 23, ?status register descriptions? on page 63 . each 4-mbit partition contains its own status register. bits sr[6:0] are unique to each partition, but sr[7], the device wsm status (dws) bit, pertains to the entire device. sr[7] provides program and erase status of the entire device. by contrast, the partition wsm status (pws) bit, sr[0], provides program and erase status of the addressed partition only. status register bits sr[6:1] present information about partition-specific program, erase, suspend, v pp , and block-lock states. table 24, ?status register device wsm and partition write status description? on page 63 presents descriptions of dws (sr[7]) and pws (sr[0]) combinations. protection register lock status partition 80h lock data protection register partition 81h - 88h register data multiple reads required to read the entire 128-bit protection register. notes: 1. the address is constructed from a base address plus an offset. for example, to read the block lock status for block number 38 in a bpd, set the address to the bba (0f8000h) plus the offset (02h), i.e. 0f8002h. then examine bit 0 of the data to determine if the block is locked. 2. see section 13.1.4, ?block lock status? on page 79 for valid lock status. table 21. device identification codes (sheet 2 of 2) item address 1 data description base offset
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 63 table 22. status register definitions dws ess es ps vpps pss dps pws 76543210 table 23. status register descriptions bit name state description 7 dws device wsm status 0 = device wsm is busy 1 = device wsm is ready sr[7] indicates erase or program completion in the device. sr[6:1] are invalid while sr[7] = 0. see table 24 for valid sr[7] and sr[0] combinations. 6 ess erase suspend status 0 = erase in progress/completed 1 = erase suspended after issuing an erase suspend command, the wsm halts and sets sr[7] and sr[6]. sr[6] remains set until the device receives an erase resume command. 5 es erase status 0 = erase successful 1 = erase error sr[5] is set if an attempted erase failed. a command sequence error is indicated when sr[7,5:4] are set. 4 ps program status 0 = program successful 1 = program error sr[4] is set if the wsm failed to program a word. 3 vpps vpp status 0 = v pp ok 1 = v pp low detect, operation aborted the wsm indicates the v pp level after program or erase completes. sr[3] does not provide continuous v pp feedback and isn?t guaranteed when v pp v pp1/2 . 2 pss program suspend status 0 = program in progress/completed 1 = program suspended after receiving a program suspend command, the wsm halts execution and sets sr[7] and sr[2]. they remain set until a resume command is received. 1 dps device protect status 0 = unlocked 1 = aborted erase/program attempt on locked block if an erase or program operation is attempted to a locked block (if wp# = v il ), the wsm sets sr[1] and aborts the operation. 0 pws partition write status 0 = this partition is busy, but only if sr[7]=0 1 = another partition is busy, but only if sr[7]=0 addressed partition is erasing or programming. in efp mode, sr[0] indicates that a data-stream word has finished programming or verifying depending on the particular efp phase. see table 24 for valid sr[7] and sr[0] combinations. table 24. status register device wsm and partition write status description dws (sr[7]) pws (sr[0]) description 00 the addressed partition is performing a program/erase operation. efp: device has finished programming or verifying data, or is ready for data. 01 a partition other than the one currently addressed is performing a program/erase operation. efp: the device is either programming or verifying data. 10 no program/erase operation is in progress in any partition. erase and program suspend bits (sr[6,2]) indicate whether other partitions are suspended. efp: the device has exited efp mode. 11 won?t occur in standard program or erase modes. efp: this combination does not occur.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 64 order number: 290701, revision: 015 10.7 clear status register the clear status register command clears the status register and leaves all partition output states unchanged. the wsm can set all status register bits and clear bits sr[7:6,2,0]. because bits sr[5,4,3,1] indicate various error conditions, they can only be cleared by the clear status register command. by allowing system software to reset these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) can be performed before reading the status register to determine error occurrence. if an error is detected, the status register must be cleared before beginning another command or sequence. device reset (rst# = v il ) also clears the status register. this command functions independently of v pp.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 65 11.0 program operations 11.1 word program when the word program command is issued, the wsm executes a sequence of internally timed events to program a word at the desired address and verify that the bits are sufficiently programmed. programming the flash array changes specifically addressed bits to 0; 1 bits do not change the memory cell contents. programming can occur in only one partition at a time. all other partitions must be in either a read mode or erase suspend mode. only one partition can be in erase suspend mode at a time. the status register can be examined for program progress by reading any address within the partition that is busy programming. however, while most status register bits are partition-specific, the device wsm status bit, sr[7], is device -specific; that is, if the status register is read from any other partition, sr[7] indicates program status of the entire device. this permits the system cpu to monitor program progress while reading the status of other partitions. ce# or oe# toggle (during polling) updates the status register. several commands can be issued to a partition that is programming: read status register, program suspend, read identifier, and read query. the read array command can also be issued, but the read data is indeterminate. after programming completes, three status register bits can signify various possible error conditions. sr[4] indicates a program failure if set. if sr[3] is set, the wsm couldn?t execute the word program command because v pp was outside acceptable limits. if sr[1] is set, the program was aborted because the wsm attempted to program a locked block. after the status register data is examined, clear it with the clear status register command before a new command is issued. the partition remains in status register mode until another command is written to that partition. any command can be issued after the status register indicates program completion. if ce# is deasserted while the device is programming, the devices will not enter standby mode until the program operation completes.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 66 order number: 290701, revision: 015 11.2 factory programming the standard factory programming mode uses the same commands and algorithm as the word program mode (40h/10h). when v pp is at v pp1 , program and erase currents are drawn through vcc. if vpp is driven by a logic signal, v pp1 must remain above the v pp1 min value to perform in- system flash modifications. when vpp is connected to a 12 v power supply, the device draws program and erase current directly from vpp. this eliminates the need for an external switching transistor to control the v pp voltage. figure 35, ?examples of vpp power supply configurations? on page 83 shows examples of flash power supply usage in various configurations. figure 26. word program flowchart suspend program loop start write 40h, word address write data word address read status register sr[7] = full program status check (if desired) program complete full program status check procedure suspend program read status register program successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 1 0 no yes v pp range error device protect error program error word program procedure sr[3] must be cleared before the wsm will allow further program attempts only the clear staus register command clears sr[4:3,1]. if an error is detected, clear the status register before attempting a program retry or other error recovery. standby standby bus operation command check sr[3] 1 = v pp error check sr[4] 1 = data program error comments repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. comments bus operation command data = 40h addr = location to program (wa) write program setup data = data to program (wd) addr = location to program (wa) write data read srd toggle ce# or oe# to update srd read check sr[7] 1 = wsm ready 0 = wsm busy standby standby check sr[1] 1 = attempted program to locked block program aborted
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 67 the 12-v v pp mode enhances programming performance during the short time period typically found in manufacturing processes; however, it is not intended for extended use.12 v may be applied to v pp during program and erase operations as specified in section 5.0, ?maximum ratings and operating conditions? on page 24 . vpp may be connected to 12 v for a total of t pph hours maximum. stressing the device beyond these limits may cause permanent damage. 11.3 enhanced factory program (efp) efp substantially improves device programming performance through a number of enhancements to the conventional 12 volt word program algorithm. efp's more efficient wsm algorithm eliminates the traditional overhead delays of the conventional word program mode in both the host programming system and the flash device. changes to the conventional word programming flowchart and internal wsm routine were developed because of today's beat-rate-sensitive manufacturing environments; a balance between programming speed and cycling performance was attained. the host programmer writes data to the device and checks the status register to determine when the data has completed programming. this modification essentially cuts write bus cycles in half. following each internal program pulse, the wsm increments the device's address to the next physical location. now, programming equipment can sequentially stream program data throughout an entire block without having to setup and present each new address. in combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to device programming. efp further speeds up programming by performing internal code verification. with this, prom programmers can rely on the device to verify that it has been programmed properly. from the device side, efp streamlines internal overhead by eliminating the delays previously associated to switch voltages between programming and verify levels at each memory-word location. efp consists of four phases: setup, program, verify and exit. refer to figure 27, ?enhanced factory program flowchart? on page 70 for a detailed graphical representation of how to implement efp. 11.3.1 efp requirements and considerations efp requirements ambient temperature: ta = 25 c 5 c v cc within specified operating range v pp within specified v pp2 range target block unlocked efp considerations block cycling below 100 erase cycles 1 rww not supported 2 efp programs one block at a time efp cannot be suspended notes: 1. recommended for optimum performance. some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. 2. code or data cannot be read from another partition during efp.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 68 order number: 290701, revision: 015 11.3.2 setup after receiving the efp setup (30h) and efp confirm (d0h) command sequence, sr[7] transitions from a 1 to a 0 indicating that the wsm is busy with efp algorithm startup. a delay before checking sr[7] is required to allow the wsm time to perform all of its setups and checks (v pp level and block lock status). if an error is detected, status register bits sr[4], sr[3], and/or sr[1] are set and efp operation terminates. note: after the efp setup and confirm command sequence, reads from the device automatically output status register data. do not issue the read status register command; it will be interpreted as data to program at wa 0 . 11.3.3 program after setup completion, the host programming system must check sr[0] to determine ?data-stream ready" status (sr[0]=0). each subsequent write after this is a program-data write to the flash array. each cell within the memory word to be programmed to 0 receives one wsm pulse; additional pulses, if required, occur in the verify phase. sr[0]=1 indicates that the wsm is busy applying the program pulse. the host programmer must poll the device's status register for the "program done" state after each data-stream write. sr[0]=0 indicates that the appropriate cell(s) within the accessed memory location have received their single wsm program pulse, and that the device is now ready for the next word. although the host may check full status for errors at any time, it is only necessary on a block basis, after efp exit. addresses must remain within the target block. supplying an address outside the target block immediately terminates the program phase; the wsm then enters the efp verify phase. the address can either hold constant or it can increment. the device compares the incoming address to that stored from the setup phase (wa 0 ); if they match, the wsm programs the new data word at the next sequential memory location. if they differ, the wsm jumps to the new address location. the program phase concludes when the host programming system writes to a different block address, and data supplied must be ffffh. upon program phase completion, the device enters the efp verify phase. 11.3.4 verify a high percentage of the flash bits program on the first wsm pulse. however, for those cells that do not completely program on their first attempt, efp internal verification identifies them and applies additional pulses as required. the verify phase is identical in flow to the program phase, except that instead of programming incoming data, the wsm compares the verify-stream data to that which was previously programmed into the block. if the data compares correctly, the host programmer proceeds to the next word. if not, the host waits while the wsm applies an additional pulse(s). the host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. it then reissues each data word in the same order as during the program phase. like programming, the host may write each subsequent data word to wa 0 or it may increment up through the block addresses.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 69 the verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be ffffh. upon completion of the verify phase, the device enters the efp exit phase. 11.3.5 exit sr[7]=1 indicates that the device has returned to normal operating conditions. a full status check should be performed at this time to ensure the entire block programmed successfully. after efp exit, any valid cui command can be issued.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 70 order number: 290701, revision: 015 figure 27. enhanced factory program flowchart efp setup efp program efp verify efp exit 1. wa 0 = first word address to be programmed within the target block. the bba (block base address) must remain constant throughout the program phase data stream; wa can be held constant at the first address location, or it can be written to sequence up through the addresses within the block. writing to a bba not equal to that of the block currently being written to terminates the efp program phase, and instructs the device to enter the efp verify phase. 2. for proper verification to occur , the verify data stream must be presented to the device in the same sequence as that of the program phase data stream. writing to a bba not equal to wa terminates the efp verify phase, and instructs the device to exit efp . 3. bits that did not fully program with the single wsm pulse of the efp program phase receive additional program-pulse attempts during the efp verify phase. the device will report any program failure by setting sr[4]=1; this check can be performed during the full status check after efp has been exited for that block, and will indicate any error within the entire data stream. commen ts bus state repeat for subsequent operations. after efp exit, a full status check can determine if any program error occurred. see the full status check procedure in the word program flowchart. write standby read write write (note 2) read standby write read standby efp setup program done? exit program phase last data? exit verify phase efp exited? write efp confirm read standby efp setup done? read standby verify stream ready? write unlock block write (note 1) standby last data? standby (note 3) verify done? sr[0]=1=n write data address = wa 0 last data? write ffffh address bba program done? read status register sr[0]=0=y y sr[0]=1=n n write data address = wa 0 verify done? last data? read status register write ffffh address bba y verify stream ready? read status register sr[7]=0=n full status check procedure operation complete read status register efp exited? sr[7]=1=y sr[0]=1=n start write 30h address = wa 0 v pp = 12v unlock block write d0h address = wa 0 efp setup done? read status register sr[7]=1=n exit n efp program efp verify efp exit efp setup enhanced factory programming procedure commen ts bus state data = 30h address = wa 0 data = d0h address = wa 0 status register check sr[7] 0 = efp ready 1 = efp not ready v pp = 12v unlock block check sr[0] 0 = program done 1 = program not done status register data = ffffh address not within same bba data = data to program address = wa 0 device automatically increments address. commen ts bus state data = word to verify address = wa 0 status register device automatically increments address. data = ffffh address not within same bba status register check sr[0] 0 = ready for verify 1 = not ready for verify check sr[0] 0 = verify done 1 = verify not done status register check sr[7] 0 = exit not finished 1 = exit completed check v pp & lock errors (sr[3,1]) data stream ready? read status register sr[0] =0=y sr[7]=0=y sr[0]=1=n standby read data stream ready? check sr[0] 0 = ready for data 1 = not ready for data status register sr[0]=0=y sr[0] =0=y efp setup time standby efp setup time standby error condition check if sr[7] = 1: check sr[3,1] sr[3] = 1 = v pp error sr[1] = 1 = locked block
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 71 12.0 program and erase operations 12.1 program/erase suspend and resume the program suspend and erase suspend commands halt an in - progress program or erase operation. the command can be issued at any device address. the partition corresponding to the command?s address remains in its previous state. a suspend command allows data to be accessed from memory locations other than the one being programmed or the block being erased. a program operation can be suspended only to perform a read operation. an erase operation can be suspended to perform either a program or a read operation within any block, except the block that is erase suspended. a program command nested within a suspended erase can subsequently be suspended to read yet another location. once a program or erase process starts, the suspend command requests that the wsm suspend the program or erase sequence at predetermined points in the algorithm. the partition that is actually suspended continues to output status register data after the suspend command is written. an operation is suspended when status bits sr[7] and sr[6] and/or sr[2] are set. to read data from blocks within the partition (other than an erase-suspended block), you can write a read array command. block erase cannot resume until the program operations initiated during erase suspend are complete. read array, read status register, read identifier (id), read query, and program resume are valid commands during program or erase suspend. additionally, clear status register, program, program suspend, erase resume, lock block, unlock block, and lock- down block are valid commands during erase suspend. to read data from a block in a partition that is not programming or erasing, the operation does not need to be suspended. if the other partition is already in read array, id, or query mode, issuing a valid address returns corresponding data. if the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. during a suspend, ce# = v ih places the device in standby state, which reduces active current. v pp must remain at its program level and wp# must remain unchanged while in suspend mode. a resume command instructs the wsm to continue programming or erasing and clears status register bits sr[2] (or sr[6]) and sr[7]. the resume command can be written to any partition. when read at the partition that is programming or erasing, the device outputs data corresponding to the partition?s last mode. if status register error bits are set, the status register can be cleared before issuing the next instruction. rst# must remain at v ih . see figure 28, ?program suspend / resume flowchart? on page 72 , and figure 29, ?erase suspend / resume flowchart? on page 73 . if a suspended partition was placed in read array, read status register, id, or query mode during the suspend, the device remains in that mode and outputs data corresponding to that mode after the program or erase operation is resumed. after resuming a suspended operation, issue the read command appropriate to the read operation. to read status after resuming a suspended operation, issue a read status register command (70h) to return the suspended partition to status mode.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 72 order number: 290701, revision: 015 figure 28. program suspend / resume flowchart r ead status register sr.7 = sr.2 = wr i te ffh susp parti tion read array data program completed done reading wr ite ffh pgm'd partition wr i te d0h any address program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure wr ite program resume data = d0h addr = suspended block (ba) bus operation command comments wr ite program suspend data = b0h addr = block to suspend (ba) standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = program suspended 0 = program completed wr ite read array data = ffh addr = any address within the suspended partition read read array data from block other than the one being programmed read status register data toggle ce# or oe# to update status register addr = suspended block (ba) pgm_sus.wm f start wr i te b0h any address program suspend read status program resume read array read array write 70h same partition wr ite read status data = 70h addr = same partition if the suspended partition was placed in read a rray mode: wr ite read status return partition to status mode: data = 70h addr = same partition write 70h same partition read status
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 73 12.2 block erase the 2-cycle block erase command sequence, consisting of erase setup (20h) and erase confirm (d0h), initiates one block erase at the addressed block. only one partition can be in an erase mode at a time; other partitions must be in a read mode. the erase confirm command internally latches the address of the block to be erased. erase forces all bits within the block to 1. sr[7] is cleared while the erase executes. figure 29. erase suspend / resume flowchart erase completed write ffh erased partition read array data 0 0 no read 1 program program loop read array data 1 yes start write b0h any address read status register sr.7 = sr.6 = write d0h any address erase resumed read or program? done? write write standby standby write erase suspend read array or program program resume data = b0h addr = any address data = ffh or 40h addr = block to program or read check sr.7 1 = w sm ready 0 = w sm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = any address bus operation command comments read status register data. toggle ce# or oe# to update status register addr = same partition read or write read array or program data from/to block other than the one being erased erase suspend / resume procedure eras_sus.wm f w rite 70h same partition write read status data = 70h addr = same partition erase resume erase suspend read status read array w rite 70h same partition read status if the suspended partition was placed in read array mode or a program loop: write read status return partition to status mode: data = 70h addr = same partition
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 74 order number: 290701, revision: 015 after writing the erase confirm command, the selected partition is placed in read status register mode and reads performed to that partition return the current status data. the address given during the erase confirm command does not need to be the same address used in the erase setup command. so, if the erase confirm command is given to partition b, then the selected block in partition b will be erased even if the erase setup command was to partition a. the 2-cycle erase sequence cannot be interrupted with a bus write operation. for example, an erase setup command must be immediately followed by the erase confirm command in order to execute properly. if a different command is issued between the setup and confirm commands, the partition is placed in read-status mode, the status register signals a command sequence error, and all subsequent erase commands to that partition are ignored until the status register is cleared. the cpu can detect block erase completion by analyzing sr[7] of that partition. if an error bit (sr[5,3,1]) was flagged, the status register can be cleared by issuing the clear status register command before attempting the next operation. the partition remains in read-status mode until another command is written to its cui. any cui instruction can follow after erasing completes. the cui can be set to read-array mode to prevent inadvertent status register reads.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 75 12.3 read-while-write and read-while-erase the intel ? wireless flash memory (w18) supports flexible multi-partition dual-operation architecture. by dividing the flash memory into many separate partitions, the device can read from one partition while programing or erasing in another partition; hence the terms, rww and rwe. both of these features greatly enhance data storage performance. figure 30. block erase flowchart sr[3,1] must be cleared before the wsm will allow further erase attempts. only the clear status register command clears sr[5:3,1]. if an error is detected, clear the status register before attempting an erase retry or other error recovery. start full erase status check procedure repeat for subsequent block erasures. full status register check can be done after each block erase or after a sequence of block erasures. no suspend erase 1 0 0 0 1 1 1 1 0 yes suspend erase loop 0 write 20h block address write d0h and block address read status register sr[7] = full erase status check (if desired) block erase complete read status register block erase successful sr[1] = erase of locked block aborted block erase procedure bus operation command comments write block erase setup data = 20h addr = block to be erased (ba) write erase confirm data = d0h addr = block to be erased (ba) read read srd toggle ce# or oe# to update srd standby check sr[7] 1 = wsm ready 0 = wsm busy bus operation command comments sr[3] = v pp range error sr[5:4] = command sequence error sr[5] = block erase error standby check sr[3] 1 = v pp error standby check sr[5:4] both 1 = command sequence error standby check sr[5] 1 = block erase error standby check sr[1] 1 = attempted erase of locked block erase aborted
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 76 order number: 290701, revision: 015 the product does not support simultaneous program and erase operations. attempting to perform operations such as these results in a command sequence error. only one partition can be programming or erasing while another partition is reading. however, one partition may be in erase suspend mode while a second partition is performing a program operation, and yet another partition is executing a read command. table 19, ?command codes and descriptions? on page 56 describes the command codes available for all functions.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 77 13.0 security modes the intel wireless flash memory offers both hardware and software security features to protect the flash data. the software security feature is used by executing the lock block command. the hardware security feature is used by executing the lock-down block command and by asserting the wp# signal. refer to figure 31, ?block locking state diagram? on page 78 for a state diagram of the flash security features. also see figure 32, ?locking operations flowchart? on page 80 . 13.1 block lock operations individual instant block locking protects code and data by allowing any block to be locked or unlocked with no latency. this locking scheme offers two levels of protection. the first allows software-only control of block locking (useful for frequently changed data blocks), while the second requires hardware interaction before locking can be changed (protects infrequently changed code blocks). the following sections discuss the locking system operation. the term ?state [abc]? specifies locking states; for example, ?state [001],? where a = wp# value, b = block lock-down status bit d1, and c = block lock status register bit d0. figure 31, ?block locking state diagram? on page 78 defines possible locking states. the following summarizes the locking functionality. ? all blocks power-up in a locked state. ? unlock commands can unlock these blocks, and lock commands can lock them again. ? the lock-down command locks a block and prevents it from being unlocked when wp# is asserted. ? locked-down blocks can be unlocked or locked with commands as long as wp# is deasserted. ? the lock-down status bit is cleared only when the device is reset or powered-down. block lock registers are not affected by the v pp level. they may be modified and read even if v pp v pplk . each block?s locking status can be set to locked, unlocked, and lock-down, as described in the following sections. see figure 32, ?locking operations flowchart? on page 80 .
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 78 order number: 290701, revision: 015 13.1.1 lock all blocks default to locked (state [x01]) after initial power-up or reset. locked blocks are fully protected from alteration. attempted program or erase operations to a locked block will return an error in sr[1]. unlocked blocks can be locked by using the lock block command sequence. similarly, a locked block?s status can be changed to unlocked or lock-down using the appropriate software commands. 13.1.2 unlock unlocked blocks (states [x00] and [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered-down. an unlocked block?s status can be changed to the locked or locked-down state using the appropriate software commands. a locked block can be unlocked by writing the unlock block command sequence if the block is not locked- down. 13.1.3 lock-down locked-down blocks (state [011]) offer the user an additional level of write protection beyond that of a regular locked block. a block that is locked-down cannot have it?s state changed by software if wp# is asserted. a locked or unlocked block can be locked-down by writing the lock-down block command sequence. if a block was set to locked-down, then later changed to unlocked, a lock- figure 31. block locking state diagram [x00] [x01] p ower-up/reset unlocked locked [011] [111] [110] locked- down 4,5 software locked [011] hardware locked 5 unlocked wp# hardware control notes: 1. [a,b,c] represents [wp#, d1, d0]. x = don?t care. 2. d1 indicates block lock-down status. d1 = ?0?, lock-down has not been issued to this block. d1 = ?1?, lock-down has been issued to this block. 3. d0 indicates block lock status. d0 = ?0?, block is unlocked. d0 = ?1?, block is locked . 4. locked-down = hardware + software locked. 5. [011] states should be tracked by system software to determine difference between hardware locked and locked-down states. software block lock (0x60/0x01) or software block unlock (0x60/0xd0) software block lock-down (0x60/0x2f) wp# hardware control
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 79 down command should be issued prior asserting wp# will put that block back to the locked-down state. when wp# is deasserted, locked-down blocks are changed to the locked state and can then be unlocked by the unlock block command. 13.1.4 block lock status every block?s lock status can be read in read identifier mode. to enter this mode, issue the read identifier command to the device. subsequent reads at bba + 02h will output that block?s lock status. for example, to read the block lock status of block 10, the address sent to the device should be 50002h (for a top-parameter device). the lowest two data bits of the read data, dq1 and dq0, represent the lock status. dq0 indicates the block lock status. it is set by the lock block command and cleared by the block unlock command. it is also set when entering the lock-down state. dq1 indicates lock-down status and is set by the lock-down command. the lock-down status bit cannot be cleared by software?only by device reset or power-down. see table 25 . 13.1.5 lock during erase suspend block lock configurations can be performed during an erase suspend operation by using the standard locking command sequences to unlock, lock, or lock-down a block. this feature is useful when another block requires immediate updating. to change block locking during an erase operation, first write the erase suspend command. after checking sr[6] to determine the erase operation has suspended, write the desired lock command sequence to a block; the lock status will be changed. after completing lock, unlock, read, or program operations, resume the erase operation with the erase resume command (d0h). if a block is locked or locked-down during a suspended erase of the same block, the locking status bits change immediately. when the erase operation is resumed, it will complete normally. locking operations cannot occur during program suspend. appendix a, ?write state machine states? on page 93 shows valid commands during erase suspend. 13.1.6 status register error checking using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. because locking changes require 2-cycle command sequences, for example, 60h followed by 01h to lock a block, following the configuration setup command (60h) with an invalid command produces a command sequence error (sr[5:4]=11b). if a lock block command error occurs during erase suspend, the device sets sr[4] and sr[5] to 1 even after the erase is resumed. when erase is table 25. write protection truth table vpp wp# rst# write protection xxv il device inaccessible v il xv ih word program and block erase prohibited xv il v ih all lock-down blocks locked xv ih v ih all lock-down blocks can be unlocked
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 80 order number: 290701, revision: 015 complete, possible errors during the erase cannot be detected from the status register because of the previous locking command error. a similar situation occurs if a program operation error is nested within an erase suspend. 13.1.7 wp# lock-down control the write protect signal, wp#, adds an additional layer of block security. wp# only affects blocks that once had the lock-down command written to them. after the lock-down status bit is set for a block, asserting wp# forces that block into the lock-down state [011] and prevents it from being unlocked. after wp# is deasserted, the block?s state reverts to locked [111] and software commands can then unlock the block (for erase or program operations) and subsequently re-lock it. only device reset or power-down can clear the lock-down status bit and render wp# ineffective. 13.2 protection register the intel wireless flash memory includes a 128-bit protection register. this protection register is used to increase system security and for identification purposes. the protection register value can match the flash component to the system?s cpu or asic to prevent device substitution. the lower 64 bits within the protection register are programmed by intel with a unique number in each flash device. the upper 64 otp bits within the protection register are left for the customer to program. once programmed, the customer segment can be locked to prevent further programming. figure 32. locking operations flowchart no optional start write 60h block address write 90h bba + 02h read block lock status locking change? lock change complete write 01,d0,2fh block address write ffh partition address yes write write write (optional) read (optional) standby (optional) write lock setup lock, unlock, or lockdown confirm read id plane block lock status read array data = 60h addr = block to lock/unlock/lock-down (ba) data = 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr = block to lock/unlock/lock-down (ba) data = 90h addr = bba + 02h block lock status data addr = bba + 02h confirm locking change on dq[1:0]. (see block locking state transitions table for valid combinations.) data = ffh addr = any address in same partition bus operation command comments locking operations procedure
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 81 note: the individual bits of the user segment of the protection register are otp, not the register in total. the user may program each otp bit individually, one at a time, if desired. after the protection register is locked, however, the entire user segment is locked and no more user bits can be programmed. the protection register shares some of the same internal flash resources as the parameter partition. therefore, rww is only allowed between the protection register and main partitions. table 26 describes the operations allowed in the protection register, parameter partition, and main partition during rww and rwe. 13.2.1 reading the protection register writing the read identifier command allows the protection register data to be read 16 bits at a time from addresses shown in table 21, ?device identification codes? on page 61 . the protection register is read from the read identifier command and can be read in any partition.writing the read array command returns the device to read-array mode. 13.2.2 programing the protection register the protection program command should be issued only at the parameter (top or bottom) partition followed by the data to be programmed at the specified location. it programs the upper 64 bits of the protection register 16 bits at a time. table 21, ?device identification codes? on page 61 shows allowable addresses. see also figure 33, ?protection register programming flowchart? on page 82 . issuing a protection program command outside the register?s address space results in a status register error (sr[4]=1). table 26. simultaneous operations allowed with the protection register protection register parameter partition array data main partitions description read see description write/erase while programming or erasing in a main partition, the protection register can be read from any other partition. reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. see description read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers from parameter partition addresses is not allowed. read read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers in a partition that is different from the one being programmed or erased, and also different from the parameter partition, is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to the parameter partition is not allowed. this is because programming of the protection register can only occur in the parameter partition, so it will exist in status mode. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. reads in other main partitions are supported.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 82 order number: 290701, revision: 015 13.2.3 locking the protection register pr-lk.0 is programmed to 0 by intel to protect the unique device number. pr-lk.1 can be programmed by the user to lock the user portion (upper 64 bits) of the protection register (see figure 34, ?protection register locking? ). this bit is set using the protection program command to program ?fffdh? into pr-lk. after pr-lk register bits are programmed (locked), the protection register?s stored values can?t be changed. protection program commands written to a locked section result in a status register error (sr[4]=1, sr[5]=1). figure 33. protection register programming flowchart full status check procedure protection program operations addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program or after a sequence of program operations. sr[3] must be cleared before the wsm will allow further program attempts. only the clear staus register command clears sr[4:3,1]. if an error is detected, clear the status register before attempting a program retry or other error recovery. yes no 1,1 1,0 1,1 protection register programming procedure start write c0h addr=prot addr write protect. register address / data read status register sr[7] = 1? full status check (if desired) program complete read srd program successful sr[4:3] = sr[4,1] = sr[4,1] = v pp range error programming error locked-register program aborted standby standby bus operation command sr[1] sr[3] sr[4] 011v pp error 0 0 1 protection register program error comments write write standby protection program setup protection program data = c0h addr = protection address data = data to program addr = protection address check sr[7] 1 = wsm ready 0 = wsm busy bus operation command comments read read srd toggle ce# or oe# to update srd standby 1 0 1 register locked; operation aborted
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 83 13.3 vpp protection the intel ? wireless flash memory (w18) provides in-system program and erase at v pp1 . for factory programming, it also includes a low-cost, backward-compatible 12 v programming feature.( section 11.2, ?factory programming? on page 66 ) the efp feature can also be used to greatly improve factory program performance as explained in section 11.3, ?enhanced factory program (efp)? on page 67 . in addition to the flexible block locking, holding the v pp programming voltage low can provide absolute hardware write protection of all flash-device blocks. if v pp is below v pplk , program or erase operations result in an error displayed in sr[3]. (see figure 35 .) note: if the v cc supply can sink adequate current, you can use an appropriately valued resistor. figure 34. protection register locking 0x84 0x88 0x85 0x81 0x80 pr lock register 0 user-programmable intel factory-programmed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 figure 35. examples of vpp power supply configurations ? 12 v fast programming ? absolute write protection with v pp v pplk system supply (note 1) vcc vpp 12 v supply ? low voltage and 12 v fast programming system supply 12 v supply ? low-voltage programming ? absolute write protection via logic signal system supply prot# (logic signal) ? low-voltage programming system supply 10k vcc vpp vcc vpp vcc vpp
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 84 order number: 290701, revision: 015 14.0 set read configuration register the set read configuration register (rcr) command sets the burst order, frequency configuration, burst length, and other parameters. a two-bus cycle command sequence initiates this operation. the read configuration register data is placed on the lower 16 bits of the address bus (a[15:0]) during both bus cycles. the set read configuration register command is written along with the configuration data (on the address bus). this is followed by a second write that confirms the operation and again presents the read configuration register data on the address bus. the read configuration register data is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). this command functions independently of the applied v pp voltage. after executing this command, the device returns to read-array mode. the read configuration register?s contents can be examined by writing the read identifier command and then reading location 05h. see table 27 and table 28 . table 27. read configuration register summary read mode res?d first access latency count wait polarity data output config wait config burst seq clock config res?d res?d burst wrap burst length rm r lc2 lc1 lc0 wt doc wc bs cc r r bw bl2 bl1 bl0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 28. read configuration register descriptions (sheet 1 of 2) bit name description 1 notes 15 rm read mode 0 = synchronous burst reads enabled 1 = asynchronous reads enabled (default) 2 14 r reserved 5 13-11 lc[2:0] first access latency count 001 = reserved 010 = code 2 011 = code 3 100 = code 4 101 = code 5 111 = reserved (default) 6 10 wt wait signal polarity 0 = wait signal is asserted low 1 = wait signal is asserted high (default) 3 9 doc data output configuration 0 = hold data for one clock 1 = hold data for two clock (default) 6 8 wc wait configuration 0 = wait asserted during delay 1 = wait asserted one data cycle before delay (default) 6 7 bs burst sequence 1 = linear burst order (default) 6 cc clock configuration 0 = burst starts and data output on falling clock edge 1 = burst starts and data output on rising clock edge (default)
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 85 5 r reserved 5 4 r reserved 5 3 bw burst wrap 0 = wrap bursts within burst length set by cr[2:0] 1 = don?t wrap accesses within burst length set by cr[2:0].(default) 2-0 bl[2:0] burst length 001 = 4-word burst 010 = 8-word burst 011 = 16-word burst 111 = continuous burst (default) 4 notes: 1. undocumented combinations of bits are reserved by intel for future implementations. 2. synchronous and page read mode configurations affect reads from main blocks and parameter blocks. status register and configuration reads support single read cycles. rcr[15]=1 disables configuration set by rcr[14:0]. 3. data is not ready when wait is asserted. 4. set the synchronous burst length. in asynchronous page mode, the page size equals four words. 5. set all reserved read configuration register bits to zero. 6. setting the read configuration register for synchronous burst-mode with a latency count of 2 (rcr[13:11] = 010), data hold for 2 clocks (rcr[9] = 1), and wait asserted one data cycle before delay (rcr[8] =1) is not supported. table 28. read configuration register descriptions (sheet 2 of 2) bit name description 1 notes
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 86 order number: 290701, revision: 015 14.1 read mode (rcr[15]) all partitions support two high-performance read configurations: synchronous burst mode and asynchronous page mode (default). rcr[15] sets the read configuration to one of these modes. status register, query, and identifier modes support only asynchronous and single-synchronous read operations. 14.2 first access latency count (rcr[13:11]) the first access latency count (rcr[13:11]) configuration tells the device how many clocks must elapse from adv# de-assertion (v ih ) before the first data word should be driven onto its data pins. the input clock frequency determines this value. see table 28, ?read configuration register descriptions? on page 84 for latency values. figure 36 shows data output latency from adv# assertion for different latencies. refer to section 14.2.1, ?latency count settings? on page 87 for latency code settings. note: other first access latency configuration settings are reserved. ) figure 36. first access latency configuration code 5 code 4 code 3 code 2 valid address valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] clk [c] d[15:0] [q] d[15:0] [q] d[15:0] [q] d[15:0] [q] figure 37. word boundary 0123456789abcdef 16 word boundary word 0 - 3 word 4 - 7 word 8 - b word c - f 4 word boundary
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 87 note: the 16-word boundary is the end of the device sense word-line. 14.2.1 latency count settings notes: 1) rcr bits[9:8] must be set to 0 for latency count of 2 . table 29. latency count setting for v ccq = 1.7 v - 1.95 v (90 nm lithography) v ccq = 1.7 - 1.95 v unit t avqv /t chqv (60ns/11ns) latency count settings 2 1 34, 5 frequency support < 40 < 61 < 66 mhz table 30. latency count setting for v ccq = 1.7 v - 2.24 v (130 nm lithography) v ccq = 1.7 - 2.24 v unit t avqv /t chqv (60ns/11ns) t avqv /t chqv (80ns/14ns) latency count settings 2 3 4, 5 2 3 4, 5 frequency support < 40 < 61 < 66 < 30 < 45 < 54 mhz table 31. latency count settings for v ccq = 1.35 v - 1.8 v (130 nm lithography) v ccq = 1.35 v - 1.8 v unit t avqv /t chqv (65ns/14ns) t avqv /t chqv (85ns/20ns) latency count settings 2 3, 4, 5 2 3, 4, 5 frequency support < 39 < 54 < 30 < 40 mhz
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 88 order number: 290701, revision: 015 14.3 wait signal polarity (rcr[10]) if the wait bit is cleared (rcr[10]=0), then wait is configured to be asserted low. this means that a 0 on the wait signal indicates that data is not ready and the data bus contains invalid data. conversely, if rcr[10] is set, then wait is asserted high. in either case, if wait is deasserted, then data is ready and valid. wait is asserted during asynchronous page mode reads. 14.4 wait signal function the wait signal indicates data valid when the device is operating in synchronous mode (rcr[15]=0), and when addressing a partition that is currently in read-array mode. the wait signal is only ?deasserted? when data is valid on the bus. when the device is operating in synchronous non-read-array mode, such as read status, read id, or read query, wait is set to an ?asserted? state as determined by rcr[10]. see figure 12, ?wait signal in synchronous non-read array operation waveform? on page 39 . when the device is operating in asynchronous page mode or asynchronous single word read mode, wait is set to an ?asserted? state as determined by rcr[10]. see figure 8, ?page-mode read operation waveform? on page 35 , and figure 6, ?asynchronous read operation waveform? on page 33 . from a system perspective, the wait signal is in the asserted state (based on rcr[10]) when the device is operating in synchronous non-read-array mode (such as read id, read query, or read status), or if the device is operating in asynchronous mode (rcr[15]=1). in these cases, the system software should ignore (mask) the wait signal, because it does not convey any useful information about the validity of what is appearing on the data bus. figure 38. example: latency count setting at 3 a max-0 (a) dq 15-0 (d/q) clk (c) ce# (e) adv# (v) r103 valid output valid output high z t add-delay t data 1nd 0st 2rd 3th 4th valid address code 3
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 89 14.5 data hold (rcr[9]) the data output configuration (doc) bit (rcr[9]) determines whether a data word remains valid on the data bus for one or two clock cycles. the processor?s minimum data set-up time and the flash memory?s clock-to-data output delay determine whether one or two clocks are needed. a doc set at 1-clock data hold corresponds to a 1-clock data cycle; a doc set at 2-clock data hold corresponds to a 2-clock data cycle. the setting of this configuration bit depends on the system and cpu characteristics. for clarification, see figure 39, ?data output configuration with wait signal delay? on page 90 . a method for determining this configuration setting is shown below. to set the device at 1-clock data hold for subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns) as an example, use a clock frequency of 66 mhz and a clock period of 15 ns. assume the data output hold time is one clock. apply this data to the formula above for the subsequent reads: 11 ns + 4 ns 15 ns this equation is satisfied, and data output will be available and valid at every clock period. if t data is long, hold for two cycles. during page-mode reads, the initial access time can be determined by the formula: t add-delay (ns) + t data (ns) + t av qv (ns) subsequent reads in page mode are defined by: t apa (ns) + t data (ns) (minimum time) table 32. wait signal conditions condition wait ce# = v ih ce# = v il tri-state active oe# no-effect synchronous array read active synchronous non-array read asserted all asynchronous read and all write asserted
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 90 order number: 290701, revision: 015 note: wait shown asserted high (rcr[10]=1). 14.6 wait delay (rcr[8]) the wait configuration bit (rcr[8]) controls wait signal delay behavior for all synchronous read-array modes. its setting depends on the system and cpu characteristics. the wait can be asserted either during, or one data cycle before, a valid output. in synchronous linear read array (no-wrap mode rcr[3]=1) of 4-, 8-, 16-, or continuous-word burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16-word boundary). if the burst start address is 4-word boundary aligned, the delay does not occur. if the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read sequence. the wait signal informs the system of this delay. 14.7 burst sequence (rcr[7]) the burst sequence specifies the synchronous-burst mode data order (see table 33, ?sequence and burst length? on page 91 ). when operating in a linear burst mode, either 4-, 8-, or 16-word burst length with the burst wrap bit (rcr[3]) set, or in continuous burst mode, the device may incur an output delay when the burst sequence crosses the first 16-word boundary. (see figure 37, ?word boundary? on page 86 for word boundary description.) this depends on the starting address. if the starting address is aligned to a 4-word boundary, there is no delay. if the starting address is the end of a 4-word boundary, the output delay is one clock cycle less than the first access latency count; this is the worst-case delay. the delay takes place only once, and only if the burst sequence crosses a 16-word boundary. the wait pin informs the system of this delay. for timing diagrams of wait functionality, see these figures: ? figure 9, ?single synchronous read-array operation waveform? on page 36 ? figure 10, ?synchronous 4-word burst read operation waveform? on page 37 figure 39. data output configuration with wait signal delay dq 15-0 [q] clk [c] valid output valid output valid output dq 15-0 [q] valid output 1 clk data hold wait (cr.8 = 1) wait (cr.8 = 0) t chqv t chqv wait (cr.8 = 0) wait (cr.8 = 1) 2 clk data hold t chtl/h note 1 note 1 note 1 note 1 valid output
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 91 ? figure 11, ?wait functionality for eowl (end-of-word line) condition waveform? on page 38 14.8 clock edge (rcr[6]) configuring the valid clock edge enables a flexible memory interface to a wide range of burst cpus. clock configuration sets the device to start a burst cycle, output data, and assert wait on the clock?s rising or falling edge. table 33. sequence and burst length start addr. (dec) burst addressing sequence (decimal) 4-word burst rcr[2:0]=001b 8-word burst rcr[2:0]=010b 16-word burst rcr[2:0]=011b continuous burst rcr[2:0]=111b linear linear linear linear wrap (rcr[3]=0) 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3...14-15-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4...15-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5...15-0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3 4-5-6-7-8-9-10... 5 5-6-7-0-1-2-3-4 5-6-7...15-0-1...4 5-6-7-8-9-10-11... 6 6-7-0-1-2-3-4-5 6-7-8...15-0-1...5 6-7-8-9-10-11-12-... 7 7-0-1-2-3-4-5-6 7-8-9...15-0-1...6 7-8-9-10-11-12-13... ... ... ... ... ... 14 14-15-0-1...13 14-15-16-17-18-19-20-... 15 15-0-1-2-3...14 15-16-17-18-19-... no-wrap (rcr[3]=1) 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3...15-16 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4...16-17 2-3-4-5-6-7-8-... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5...17-18 3-4-5-6-7-8-9-... 4 4-5-6-7-8-9-10-11 4-5-6...18-19 4-5-6-7-8-9-10... 5 5-6-7-8-9-10-11-12 5-6-7...19-20 5-6-7-8-9-10-11... 6 6-7-8-9-10-11-12-13 6-7-8...20-21 6-7-8-9-10-11-12-... 7 7-8-9-10-11-12-13-14 7-8-9...21-22 7-8-9-10-11-12-13... ... ... ... ... ... 14 14-15...28-29 14-15-16-17-18-19-20-... 15 15-16...29-30 15-16-17-18-19-20-21-...
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 92 order number: 290701, revision: 015 14.9 burst wrap (rcr[3]) the burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within the burst- length boundary or whether they cross word-length boundaries to perform linear accesses. no- wrap mode (rcr[3]=1) enables wait to hold off the system processor, as it does in the continuous burst mode, until valid data is available. in no-wrap mode (rcr[3]=0), the device operates similarly to continuous linear burst mode but consumes less power during 4-, 8-, or 16- word bursts. for example, if rcr[3]=0 (wrap mode) and rcr[2:0] = 1h (4-word burst), possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. if rcr[3]=1 (no-wrap mode) and rcr[2:0] = 1h (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. rcr[3]=1 not only enables limited non- aligned sequential bursts, but also reduces power by minimizing the number of internal read operations. setting rcr[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst sequences. however, significantly more power may be consumed. the 1-2-3-4 sequence, for example, consumes power during the initial access, again during the internal pipeline lookup as the processor reads word 2, and possibly again, depending on system timing, near the end of the sequence as the device pipelines the next 4-word sequence. rcr[3]=1 while in 4-word burst mode (no-wrap mode) reduces this excess power consumption. 14.10 burst length (rcr[2:0]) the burst length bit (bl[2:0]) selects the number of words the device outputs in synchronous read access of the flash memory array. the burst lengths are 4-word, 8-word, 16-word, and continuous word. continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see table 33, ?sequence and burst length? on page 91 ). when a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the ?burstable? address space.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 93 appendix a write state machine states this table shows the command state transitions based on incoming commands. only one partition can be actively programming or erasing at a time. figure 40. write state machine ? next state table (sheet 1 of 2) chip next state after command input read array (3) program setup (4,5) erase setup (4,5) enhanced factory pgm setup (4) be confirm, p/e resume, ulb confirm (9) program/ erase suspend read status clear status register (6) read id/query (ffh) (10h/40h) (20h) (30h) (d0h) (b0h) (70h) (50h) (90h, 98h ) ready ready program setup erase setup efp setup ready lock/cr setup ready (lock error) ready ready (lock error) setup otp busy busy setup program busy busy program busy pgm susp program busy suspend program suspend pgm busy program suspend setup ready (error) erase busy ready (error) busy erase busy erase susp erase busy suspend erase suspend pgm in erase susp setup erase suspend erase busy erase suspend setup program in erase suspend busy busy program in erase suspend busy pgm susp in erase susp program in erase suspend busy suspend program suspend in erase suspend pgm in erase susp busy program suspend in erase suspend erase suspend (lock error) erase susp erase suspend (lock error) setup ready (error) efp busy ready (error) efp busy efp busy (7) efp verify verify busy (7) output next state after command input status status status id/query write state machine (wsm) next state table output next state table (1) lock/cr setup, lock/cr setup in erase susp otp busy current chip state (8) ready, pgm busy, pgm suspend, erase busy, erase suspend, pgm in erase susp busy, pgm susp in erase susp pgm setup, erase setup, otp setup, pgm in erase susp setup, efp setup, efp busy, verify busy lock/cr setup in erase suspend erase program program in erase suspend otp enhanced factory program output does not change array (3) status output does not change status
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 94 order number: 290701, revision: 015 notes: 1. the output state shows the type of data that appears at the outputs if the partition address is the same as the command address. a partition can be placed in read array, read status or read id/cfi, depending on the command issued. each partition stays in its last output state (array, id/cfi or status) until a new command changes it. the next wsm state does not depend on the partition's output state. for example, if partition #1's output state is read array and partition #4's output state is read status, every read from partition #4 (without issuing a new command) outputs the status register. figure 40. write state machine ? next state table (sheet 2 of 2) chip next state after command input lock, unlock, lock-down, cr setup (5) otp setup (5) lock block confirm (9) lock- down block confirm (9) write cr confirm (9) enhanced fact pgm exit (blk add <> wa0) illegal commands or efp data (2) (60h) (c0h) (01h) (2fh) (03h) (xxxxh) (other codes) ready lock/cr setup otp setup ready lock/cr setup ready (lock error) ready ready ready ready (lock error) setup otp busy busy ready setup program busy n/a busy program busy ready suspend program suspend setup ready (error) busy erase busy erase busy ready suspend lock/cr setup in erase susp erase suspend setup program in erase suspend busy busy program in erase suspend busy erase suspend suspend program suspend in erase suspend erase suspend (lock error) erase susp erase susp erase susp erase suspend (lock error) setup ready (error) efp busy efp busy (7) efp verify efp busy (7) efp verify verify busy (7) ready efp verify (7) ready output next state after command input status status array status write state machine (wsm) next state table output next state table (1) program erase program in erase suspend current chip state (8) otp lock/cr setup in erase suspend enhanced factory program output does not change output does not change wsm operation completes n/a n/a n/a n/a output does not change array status pgm setup, erase setup, otp setup, pgm in erase susp setup, efp setup, efp busy, verify busy lock/cr setup, lock/cr setup in erase susp otp busy ready, pgm busy, pgm suspend, erase busy, erase suspend, pgm in erase susp busy, pgm susp in erase susp
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 95 2. illegal commands are those not defined in the command set. 3. all partitions default to read array mode at power-up. a read array command issued to a busy partition results in undermined data when a partition address is read. 4. both cycles of 2 cycles commands should be issued to the same partition address. if they are issued to different partitions, the second write determines the active partition. both partitions will output status information when read. 5. if the wsm is active, both cycles of a 2 cycle command are ignored. this differs from previous intel devices. 6. the clear status command clears status register error bits except when the wsm is running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, efp modes) or suspended (erase suspend, pgm suspend, pgm suspend in erase suspend). 7. efp writes are allowed only when status register bit sr.0 = 0. efp is busy if block address = address at efp confirm command. any other commands are treated as data. 8. the "current state" is that of the wsm, not the partition. 9. confirm commands (lock block, unlock block, lock-down block, configuration register) perform the operation and then move to the ready state. 10. in erase suspend, the only valid two cycle commands are "program word", "lock/unlock/lockdown block", and "cr write". both cycles of other two cycle commands ("oem cam program & confirm", "program otp & confirm", "efp setup & confirm", "erase setup & confirm") will be ignored. in program suspend or program suspend in erase suspend, both cycles of all two cycle commands will be ignored.
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 96 order number: 290701, revision: 015 appendix b common flash interface (cfi) this appendix defines the data structure or ?database? returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. b.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq0-7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii ?q? in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word-wide devices is always ?00h,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 34. summary of query structure output as a function of device and mode device hex offset hex code ascii value device addresses 00010 51 ?q? 00011 52 ?r? 00012 59 ?y?
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 97 b.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? the structure sub-sections and address locations are summarized below. table 36. query structure notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1?s beginning location when the block size is 32k-word). 3. offset 15 defines ?p? which points to the primary intel-specific extended query table. b.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. table 35. example of query structure output of x16 and x8 devices word addressing byte addressing offset hex code value offset hex code value a x - a 0 d 16 - d 0 a x - a 0 d 7 - d 0 00010h 0051 ?q? 00010h 51 ?q? 00011h 0052 ?r? 00011h 52 ?r? 00012h 0059 ?y? 00012h 59 ?y? 00013h p id lo p rvendor 00013h p id lo p rvendor 00014h p id hi id # 00014h p id lo id # 00015h p lo p rvendor 00015h p id hi id # 00016h p hi tbladr 00016h ... ... 00017h a id lo altvendor 00017h ... ... 00018h a id hi id # 00018h ... ... offset sub-section name description (1) 00000h manufacturer code 00001h device code (ba+2)h (2) block status register block-specific information 00004-fh reserved reserved for vendor-specific information 00010h cfi query identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primary intel-specific extended query table vendor-defined additional information specific to the primary vendor algorithm
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 98 order number: 290701, revision: 015 block erase status (bsr.1) allows system software to determine the success of the last block erase operation. bsr.1 can be used just after power-up to verify that the vcc supply was not accidentally removed during an erase operation. table 37. block status register notes: 1. ba = block address beginning location (i.e., 08000h is block 1?s beginning location when the block size is 32k-word). b.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). offset length description add. value (ba+2)h (1) 1 block lock status register ba+2 --00 or --01 ba+2 (bit 0): 0 or 1 ba+2 (bit 1): 0 or 1 bsr 2?7: reserved for future use ba+2 (bit 2?7): 0 bsr.0 block lock status 0 = unlocked 1 = locked bsr.1 block lock-down status 0 = not locked down 1 = locked down
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 99 table 39. system interface information table 38. cfi identification offset length description addr. hex code value 10h 3 query-unique ascii string ?qry? 10: 11: 12: --51 --52 --59 ?q? ?r? ?y? 13h 2 primary vendor command set and control interface id code. 16-bit id code for vendor-specific algorithms. 13: 14: --03 --00 ? 15h 2 extended query table primary algorithm address 15: 16: --39 --00 ? 17h 2 alternate vendor command set and control interface id code. 0000h means no second vendor-specified algorithm exists. 17: 18: --00 --00 ? 19h 2 secondary algorithm extended query table address. 0000h means none exists. 19: 1a: --00 --00 ? offset length description add. hex code valu e 1bh 1 1b: --17 1.7v 1ch 1 1c: --19 1.9v 1dh 1 1d: --b4 11.4 v 1eh 1 1e: --c6 12.6 v 1fh 1 ?n? such that typical single word program time-out = 2 n -sec 1f: --04 16s 20h 1 ?n? such that typical max. buffer write time-out = 2 n -sec 20: --00 na 21h 1 ?n? such that typical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 ?n? such that typical full chip erase time-out = 2 n m-sec 22: --00 na 23h 1 ?n? such that maximum word program time-out = 2 n times typical 23: --04 256 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --00 na 25h 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --03 8s 26h 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 100 order number: 290701, revision: 015 b.5 device geometry definition table 40. device geometry definition offset length description code 27h 1 ?n? such that device size = 2 n in number of bytes 27: see table below 76543210 28h 2 ????x64x32x16x828:--01x16 15 14 13 12 11 10 9 8 ????????29:--00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --00 0 2b: --00 2ch 1 2c: 2dh 4 erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 erase block region 2 information 31: bits 0?15 = y, y+1 = number of identical-size erase blocks 32: bits 16?31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 reserved for future erase block region information 35: 36: 37: 38: see table below see table below see table below see table below number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: address 32 mbit ?b ?t ?b ?t ?b ?t 27: --16 --16 --17 --17 --18 --18 28: --01 --01 --01 --01 --01 --01 29: --00 --00 --00 --00 --00 --00 2a: --00 --00 --00 --00 --00 --00 2b: --00 --00 --00 --00 --00 --00 2c: --02 --02 --02 --02 --02 --02 2d: --07 --3e --07 --7e --07 --fe 2e: --00 --00 --00 --00 --00 --00 2f: --20 --00 --20 --00 --20 --00 30: --00 --01 --00 --01 --00 --01 31: --3e --07 --7e --07 --fe --07 32: --00 --00 --00 --00 --00 --00 33: --00 --20 --00 --20 --00 --20 34: --01 --00 --01 --00 --01 --00 35: --00 --00 --00 --00 --00 --00 36: --00 --00 --00 --00 --00 --00 37: --00 --00 --00 --00 --00 --00 38: --00 --00 --00 --00 --00 --00 64 mbit 128 mbit
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 101 b.6 intel-specific extended query table table 41. primary vendor-specific extended query offset (1) length description hex p = 39h (optional flash features and commands) add. code value (p+0)h 3 primary extended query table 39: --50 "p" (p+1)h unique ascii string ?pri? 3a: --52 "r" (p+2)h 3b: --49 "i" (p+3)h 1 major version number, ascii 3c: --31 "1" (p+4)h 1 minor version number, ascii 3d: --33 "3" (p+5)h 4 optional feature and command support (1=yes, 0=no) 3e: --e6 (p+6)h bits 10?31 are reserved; undefined bits are ?0.? if bit 31 is 3f: --03 (p+7)h ?1? then another 31 bit field of optional features follows at 40: --00 (p+8)h the end of the bit?30 field. 41: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 1 yes (p+9)h 1 42: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h 2 block status register mask 43: --03 (p+b)h bits 2?15 are reserved; undefined bits are ?0? 44: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes (p+c)h 1 45: --18 1.8v (p+d)h 1 46: --c0 12.0 v supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 102 order number: 290701, revision: 015 table 43. burst read information for non-muxed device table 44. partition and erase-block region information table 42. protection register information offset p = 39h lengt h description (optional flash features and commands) add. hex code value (p + e)h 1 number of protectuib register fields in jedec id space. ?00h? indicates that 256 protection fields are available. 47: --01 1 (p + e)h (p + 10)h (p + 11)h (p + 12)h 4 protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes, some are pre-programmed with device-unique serial numbers. others are user-programmable. bits are 0-15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user- programmable: ? bits 0-7 = lock/bytes jedec-plane physical low address ? bites 8-15 = lock/bytes jedec-plane physical high address ? bits 16-23 = ?n? such that 2n = factory pre-programmed bytes ? bits 24-31 = ?n? such that 2n = user-programmable bytes 48: 49: 4a: 4b: --80 --00 --03 --03 80h 00h 8 byte 8 byte offset (1) length description hex p = 39h (optional flash features and commands) add. code value (p+13)h 1 4c: --03 8 byt e (p+14)h 1 4d: --04 4 (p+15)h 1 4e: --01 4 (p+16)h 1 synchronous mode read capability configuration 2 4f: --02 8 (p+17)h 1 synchronous mode read capability configuration 3 50: --03 16 (p+18)h 1 synchronous mode read capability configuration 4 51: --07 con t page mode read capability bits 0?7 = ?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. synchronous mode read capability configuration 1 bits 3?7 = reserved bits 0?2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0?2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. offset (1) see table below p = 39h description address bottom top (optional flash features and commands) len bot top (p+19)h (p+19)h 1 52: 52: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 103 table 45. partition region 1 information offset (1) see table below p = 39h description address bottom top (optional flash features and commands) len bot top (p+1a)h (p+1a)h number of identical partitions within the partition region 2 53: 53: (p+1b)h (p+1b)h 54: 54: (p+1c)h (p+1c)h 1 55: 55: (p+1d)h (p+1d)h 1 56: 56: (p+1e)h (p+1e)h 1 57: 57: (p+1f)h (p+1f)h 1 58: 58: (p+20)h (p+20)h partition region 1 erase block type 1 information 4 59: 59: (p+21)h (p+21)h bits 0?15 = y, y+1 = number of identical-size erase blocks 5a: 5a: (p+22)h (p+22)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 5b: 5b: (p+23)h (p+23)h 5c: 5c: (p+24)h (p+24)h partition 1 (erase block type 1) 25d:5d: (p+25)h (p+25)h minimum block erase cycles x 1000 5e: 5e: (p+26)h (p+26)h 1 5f: 5f: (p+27)h (p+27)h 1 60: 60: (p+28)h partition region 1 erase block type 2 information 4 61: (p+29)h bits 0?15 = y, y+1 = number of identical-size erase blocks 62: (p+2a)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 63: (p+2b)h (bottom parameter device only) 64: (p+2c)h partition 1 (erase block type 2) 2 65: (p+2d)h minimum block erase cycles x 1000 66: (p+2e)h 167: (p+2f)h 168: simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations number of program or erase operations allowed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations partition 1 (erase block type 1) bits per cell; internal ecc bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 1) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use partition 1 (erase block type 2) bits per cell bits 0?3 = bits per cell in erase region bit 4 = reserved for ?internal ecc used? (1=yes, 0=no) bits 5?7 = reserve for future use partition 1 (erase block type 2) pagemode and synchronous mode capabilities defined in table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes)
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 104 order number: 290701, revision: 015 notes: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. tpd - top parameter device; bpd - bottom parameter device. 3. partition: each partition is 4-mbit in size. it can contain main blocks or a combination of both main and parameter blocks. 4. partition region: symmetrical partitions form a partition region. there are two partition regions: a contains all the partitions that are made up of main blocks only; b contains the partition made up of the parameter and the main blocks. table 46. partition and erase block region information address 32 mbit ?b ?t ?b ?t ?b ?t 52: --02 --02 --02 --02 --02 --02 53: --01 --07 --01 --0f --01 --1f 54: --00 --00 --00 --00 --00 --00 55: --11 --11 --11 --11 --11 --11 56: --00 --00 --00 --00 --00 --00 57: --00 --00 --00 --00 --00 --00 58: --02 --01 --02 --01 --02 --01 59: --07 --07 --07 --07 --07 --07 5a: --00 --00 --00 --00 --00 --00 5b: --20 --00 --20 --00 --20 --00 5c: --00 --01 --00 --01 --00 --01 5d: --64 --64 --64 --64 --64 --64 5e: --00 --00 --00 --00 --00 --00 5f: --01 --01 --01 --01 --01 --01 60: --03 --03 --03 --03 --03 --03 61: --06 --01 --06 --01 --06 --01 62: --00 --00 --00 --00 --00 --00 63: --00 --11 --00 --11 --00 --11 64: --01 --00 --01 --00 --01 --00 65: --64 --00 --64 --00 --64 --00 66: --00 --02 --00 --02 --00 --02 67: --01 --06 --01 --06 --01 --06 68: --03 --00 --03 --00 --03 --00 69: --07 --00 --0f --00 --1f --00 6a: --00 --01 --00 --01 --00 --01 6b: --11 --64 --11 --64 --11 --64 6c: --00 --00 --00 --00 --00 --00 6d: --00 --01 --00 --01 --00 --01 6e: --01 --03 --01 --03 --01 --03 6f: --07 --07 --07 --07 --07 --07 70: --00 --00 --00 --00 --00 --00 71: --00 --20 --00 --20 --00 --20 72: --01 --00 --01 --00 --01 --00 73: --64 --64 --64 --64 --64 --64 74: --00 --00 --00 --00 --00 --00 75: --01 --01 --01 --01 --01 --01 76: --03 --03 --03 --03 --03 --03 64mbit 128mbit
intel ? wireless flash memory (w18) datasheet intel ? wireless flash memory (w18) 07-dec-2005 order number: 290701, revision: 015 105 appendix c ordering information figure 41. vf bga ordering information p ackage: g e = vf bga, leaded p h = vf bga, pb-free p roduct line designator: f or all intel flash products d evice density: 3 20 = 32mbit 6 40 = 64mbit 1 28 = 128mbit product family: w18 = intel ? wireless flas h memory parameter location: t = top parameter b = bottom parameter process identifier: c = 180 nm d = 130 nm e = 90 nm access speed (ns) (60,80) g e 2 8 f 6 4 0 w 1 8 t e 6 0 figure 42. scsp ordering information p ackage: r d = scsp, leaded p f = scsp, pb-free p roduct line: 4 8f = flash only f lash density: 0 = no die 3 = 128 mbit p roduct family designator: w = intel ? wireless flash memory voltage: y = 1.8 volt i/o ballout indicator: q= quad+ parameter location : t = top parameter b = bottom parameter device details: 0 = initial version flash 1 & 2 flash 3 & 4 flash 1 flash 2 flash 3 flash 4 r d 4 8 f 3 0 0 0 w 0 y b q 0
intel ? wireless flash memory (w18) 07-dec-2005 intel ? wireless flash memory (w18) datasheet 106 order number: 290701, revision: 015 table 47. w18 family: available product ordering information i/o voltage (v) flash density package part number size (mm) ballout name ballout type 1.8 32 mbit 9x7.7x1.0 vf bga leaded ge28f320w18td60 ge28f320w18bd60 ge28f320w18te60 ge28f320w18be60 lead free ph28f320w18td60 ph28f320w18bd60 PH28F320W18TE60 ph28f320w18be60 64 mbit 9x7.7x1.0 vf bga leaded ge28f640w18td60 ge28f640w18bd60 ge28f640w18te60 ge28f640w18be60 ge28f640w18td80 ge28f640w18bd80 lead free ph28f640w18td60 ph28f640w18bd60 ph28f640w18te60 ph28f640w18be60 128 mbit 9x11x1.0 vf bga leaded ge28f128w18td60 ge28f128w18bd60 lead free ph28f128w18td60 ph28f128w18bd60 10x8x1.2 scsp leaded rd48f3000w0ytq0 rd48f3000w0ybq0 lead free pf48f3000w0ytq0 pf48f3000w0ybq0

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